erratum | Error & warning handling for R inspired by go | Code Analyzer library
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kandi X-RAY | erratum Summary
Docs | Quick start | Install. Erratum handles errors and warnings in a manner inspired by Go's standard error library.
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QUESTION
Intel recommends using instruction prefixes to mitigate the performance consequences of JCC Erratum.
MSVC if compiled with /QIntel-jcc-erratum follows the recommendation, and inserts prefixed instructions, like this:
ANSWER
Answered 2021-Dec-21 at 16:31A NOP is a separate instruction that had to decode and go through the pipeline separately. It's always better to pad instructions with prefixes to achieve desired alignment, not insert NOPs, as discussed in What methods can be used to efficiently extend instruction length on modern x86? (but only in ways that don't cause major stalls on some CPUs which can't handle large numbers of prefixes).
Perhaps Intel considered it worth the effort for toolchains to do it this way for this case since this would actually be inside inner loops, not just a NOP outside an inner loop. (And tacking on prefixes to one previous instruction is relatively simple.)
I now have some data point. The result of benchmarking for /QIntel-jcc-erratum on AMD FX 8300 is bad.
The slowdown is by a decimal order of magnitude for a specific benchmark, where the benefit on Intel Skylake for the same benchmark is about 20 percent. This aligns with Peter's comments:
I checked Agner Fog's microarch guide, and AMD Zen has no problem with any number of prefixes on a single instruction, like mainstream Intel since Core2. AMD Bulldozer-family has a "very large" penalty for decoding instructions with more than 3 prefixes, like 14-15 cycles for 4-7 prefixes
It's somewhat valid to consider Bulldozer-family obsolete enough to not care much about it, although there are still some APU desktops and laptops around for sure, but they'd certainly show large regressions in loops where the compiler put 4 or more prefixes on one instruction inside a hot inner loop (including existing prefixes like REX or 66h). Much worse than the 3% for MITE legacy decode on SKL.
Though indeed Bulldozer-family is obsolete-ish, I don't think I can afford this much of an impact. I'm also afraid of other CPUs that may choke with extra prefixes the same way. So the conclusion for me is not to use /QIntel-jcc-erratum for generally-targeted software. Unless it is enabled in specific translation units and dynamic dispatch to there is made, which is too much of the trouble most of the time.
One thing that probably safe to do on MSVC is to stop using /Os flag . It was discovered that /Os flag at least:
- Avoids jump tables in favor of conditional jumps
- Avoids loop start padding
Try the following example (https://godbolt.org/z/jvezPd9jM):
QUESTION
I notice that in the Cortex-M3 that the LDRD (load double word) is listed in the errata, but I'm not finding similar for Cortex-M4, and at any rate, there does not appear to be an interrupt occurring during execution. I'm working with an M4 microcontroller, and passing data to/from a host. It's handy to work with the data in the shape the host (same architecture) deals with it - for example, if the host passes an unsigned 16-bit integer, I accept it as a uint16_t, even though it is in two byte array data_in:
ANSWER
Answered 2021-Apr-30 at 14:03In the ARMv7M architecture reference manual, section A3.2.1 "Alignment behavior" it says:
The following data accesses always generate an alignment fault:
- Non halfword-aligned LDREXH and STREXH .
- Non word-aligned LDREX and STREX .
- Non word-aligned LDRD , LDMIA , LDMDB , POP , LDC , VLDR , VLDM , and VPOP .
- Non word-aligned STRD , STMIA , STMDB , PUSH , STC , VSTR , VSTM , and VPUSH .
So unless you know that data_in is at-least 32-bit aligned, you can't cast it to (uint64_t*) and expect it to work.
QUESTION
Intel pushed microcode update to fix error called "Jump Conditional Code (JCC) Erratum". The update microcode caused some operation to be inefficient due to disabling putting code to ICache under certain conditions.
Published document, titled Mitigations for Jump Conditional Code Erratum lists not only JCC, it lists: unconditional jumps, conditional jumps, macro-fused conditional jumps, calls, and return.
MSVC switch /QIntel-jcc-erratum documentation mentions:
Under /QIntel-jcc-erratum, the compiler detects jump and macro-fused jump instructions that cross or end on a 32-byte boundary.
The questions are:
- Are there reasons to treat JCC separately from other jumps?
- Are there reasons to treat macro-fused JCC mentioned separately from other JCC?
ANSWER
Answered 2020-Aug-07 at 20:35Macro-fused jumps have to be mentioned separately because it means the whole cmp/jcc or whatever is vulnerable to this slowdown if the cmp touches the boundary when the jcc itself doesn't. Because the uop cache would have a single uop for both those x86 machine instructions together, with the start address of the non-jump instruction.
If everyone only said "jumps", you'd expect that only the JCC / JMP / CALL / RET itself had to avoid touching a 32B boundary. So it's a good thing to highlight the interaction with macro-fusion.
This slowdown (for all jumps) is the result of a microcode mitigation / workaround for a hardware design flaw. Not being able to uop-cache cache jumps that touch a 32-byte boundary is not the original erratum, it's a side effect of the cure.
That original erratum description doesn't say anything about affecting only conditional branches. Even if it was only conditional branches that were a real problem, perhaps the best way Intel could find to make it safe with a microcode update unfortunately affected all jumps.
For example, in Skylake-Xeon (SKX), the original erratum is documented as SKX102 in Intel's "spec update" errata list for that uarch:
SKX102. Processor May Behave Unpredictably on Complex Sequence of Conditions Which Involve Branches That Cross 64 Byte Boundaries
Problem: Under complex micro-architectural conditions involving branch instructions bytes that span multiple 64 byte boundaries (cross cache line), unpredictable system behavior may occur.
Implication: When this erratum occurs, the system may behave unpredictably.
Workaround: It is possible for BIOS to contain a workaround for this erratum. [i.e. a microcode update]
Status: No fix.
I suspect the "JCC erratum" name caught on because most branches in "hot" code paths are conditional. Compilers can usually avoid putting unconditional taken branches in the fast path. So it's likely that people noticed the performance problem with JCC instructions first, and that name simply stuck even though it's not accurate.
BTW, 32-byte aligned routine does not fit the uops cache has a screenshot of the relevant diagram from the Intel PDF you linked about, and some other links and details about performance effects.
QUESTION
I'm having trouble copying a file on a Google Drive using v3 of the Google Drive API for Java.
The file in question is on a shared team drive, and I'm reading in credentials that are associated with a service account. The service account has "manager" access to the drive in question.
Here is my code that is trying to copy the file. It's in Scala, rather than Java, but hopefully it will be clear enough anyway, even if you don't know Scala. (In case you don't already know, Scala is a programming language that targets the JVM and interoperates with Java in a relatively painless manner.)
...ANSWER
Answered 2020-Jul-23 at 10:18.setSupportsAllDrives(true)
See parameters of Files: copy:
supportsAllDrives
Whether the requesting application supports both My Drives and shared drives. (Default: false)
- Mind that by default the file will be copied into the same (shared) folder / drive where the original file is located
- If you want to copy it elsewhere, you nedd to specify the
parents[]parameter
QUESTION
I have a Raspberry Pi 4 and I need to create an image of an openwrt-based system with support for AWUS036ACH.
I have completed the following steps:
- Created his own package for buildroot tools, the makefile of which contains a "Build/Compile" section:
ANSWER
Answered 2020-Apr-21 at 06:47It look like you are using the host toolchain (at least ld). Your CROSS_COMPILE option is empty.
have you take a look at https://buildroot.org/downloads/manual/manual.html#_infrastructure_for_packages_building_kernel_modules
QUESTION
I'm building a couple of Python libraries/apps. I'm still relatively new to Python, and I struggle a lot with the import system. I think I've got a good handle on it for intra-app/module imports, but I'm now trying to import modules from a library I'm building for public release into my other project, and I flat out can't get it to recognize submodules for import.
The library in question is https://github.com/utoxin/PyChance
And I'm trying to import the 'SimpleTable' class from pychance/data/simpletable_class.py. I've tried multiple different import statements, and even different organizations of the library including moving simpleable.py up to the top-level directory, and various import lines in the library's init.py files.
My IDE suggests
...ANSWER
Answered 2020-Mar-14 at 21:38According to the packaging of PyChance, the 2 following imports are functionals:
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