Arachne | Core aware thread management system

While going through the router.cc the file of arcahne-pnr, I am unable to understand, how are the programmable interconnect pins PIPs routed? Does it seem PLL is representing the PIPs in the code? Could somebody help to make me clear, what corresponds to PIP in arachne-pnr? Thanks

i m new to yosys and arachne-pnr. Here is the snippet from .asc and .icebox_explain. I could not understand how the bits of LC_5 are derived from .logic_tile 1 11.

example.v

I wanted to know the internal clk reference pin number to be added for arachne-pnr pcf file. I am synthesizing for Alchitry Cu Board having the iCE40 HX8k chip (supported by yosis and arachne). I couldnt understand the correlation between pin number in pcf file to pin of the chip...

If someone could give me an example pcf file for say a DFF (something using clock), I will figure out the remaining. I have searched for this in google but was unsuccessful.

I saw some reference on .gate... command but didn't understand whether it should be added to pcf file or some other file and compiled for clk output. If so, please give me that command example

Sorry, for the long question. Any help will be much appreciated.

Thanks, Bharat

I am creating a program that needs to have an array of 100 strings. Each string refers to a mythological god in the game SMITE. This god has 3 important attributes that determine what items the god is allowed to use.

1: ability Class: warrior, mage, guardian, hunter, assassin.

2: Range: Melee or Range.

3: Damage type: Magical or Physical

Basically this program gets a random god, and builds 6 random items from the allowed list it can access based on these attributes.

These attributes will be looked at in order to determine what items the god is allowed to use. there will be around 150 items, and these items are only able to be used by a specific class, range, and damage type.

I have a current solution that works but unfortunately i have to create an entire string array with all of the gods that belong to each type. For example i create an array with 50 magical gods, then an array with 20 mages. in order to determine which items that god can use i am checking the randomly generated god String against all of the arrays that determine its type, and if it is found then flag that type. I am wondering if it is possible to store these gods as objects with all of these identifiers. Example. The god "Anubis" would have the mage ability class, the ranged range type, and the magical damage type, all stored in the one object that defines Anubis. That way i would not have to create tons of long Arrays full of god names and check them against each other. If this is possible please someone help. I am currently in a programming class for C++ and we have not covered OOP but i am somewhat familiar with it because of python.

When I synthesize an empty circuit using Yosys and arachne-pnr, I get a few irregular bits:

Is the correspondence between the I/O blocks of an iCE40 FPGA and the pins of the package they drive documented somewhere?

The I/O tile documentation of Project IceStorm gives a list of I/O blocks, and for each block where its IE and REN bits are located in the bitstream. A few blocks are missing from this list:

I'm trying to understand the bitstreams generated by Yosys/arachne-pnr as described on http://www.clifford.at/icestorm/:

The recommended approach for learning how to use this documentation is to synthesize very simple circuits using Yosys and Arachne-pnr, run the icestorm tool icebox_explain on the resulting bitstream files, and analyze the results using the HTML export of the database mentioned above. icebox_vlog can be used to convert the bitstream to Verilog. The output file of this tool will also outline the signal paths in comments added to the generated Verilog code.

In order to understand the effect a change in the bitstream has, it would be helpful if I could change the .ex file and convert it back to an ASCII bitstream (instead of having to identify the bit manually) for uploading to the FPGA. Is there a way to do so?

I'm a bit concerned about damaging the FPGA with an invalid bitstream. Are there situations where this is known to happen? Is there a way to simulate a bitstream?

Also, it would be helpful to have some kind of “higher-level” explanation format which e.g. shows the IE/REN bits on the I/O blocks to which they correspond, not the one on which they have to be set in the bitstream. Is there such a format?

I know of the possibility to generate an equivalent Verilog circuit, but the problem with this is that it doesn't usually allow me a lossless round-trip back into a bitstream. Is there a way to generate an equivalent Verilog circuit which (e.g. by instantiating the blocks explicitly) yields the exact same bitstream when processed with Yosys/arachne-pnr?