AutoSA | AutoSA: Polyhedral-Based Systolic Array Compiler

We offer a Docker image for quick start. Let's try one small example. The input code can be found at ${AUTOSA_ROOT}/autosa_tests/mm/kernel.c. The code region to be transformed to systolic array is annotated using a pair of pragmas scop and endscop. Run the following command to compile generate a systolic array. The generated code can be found in ${AUTOSA_ROOT}/autosa.tmp/output/src/. For detailed explaination of each AutoSA compilation option, please run. or refer to AutoSA Compilation Options. To generate the final bitsteam, set up your local Vitis development kit first. Then execute the makefile to build the design. The connectivity.cfg describes the DRAM port mapping. For more details about how to change the DRAM port mapping, please refer to the Xilinx tutorials. AutoSA also supports generate HLS projects. Add the flag. to the command when compiling the program. AutoSA will generate an HLS host file ${AUTOSA_ROOT}/autosa.tmp/output/src/kernel_host.cpp instead of the OpenCL host file generated in the previous step. To build the HLS project, run the following commands. For more detailed instructions on using AutoSA, please refer to the AutoSA Documentation.
Generating HLS C Code.
Generating FPGA Bitstream
MODE := hw_emu: Set the build configuration mode to HW Emulation, other modes: sw_emu|hw
PLATFORM := xilinx_u250_xdma_201830_2: Select the target platform
KERNEL_SRC := src/kernel_kernel.cpp: List the kernel source files
HOST_SRC := src/kernel_host.cpp: List the host source files
Verifying Designs Using Xilinx HLS