gem5 | Modified gem5 with new , machine learning based cache

by bxshi C++ Version: Current License: Non-SPDX

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kandi X-RAY | gem5 Summary

gem5 is a C++ library. gem5 has no bugs, it has no vulnerabilities and it has low support. However gem5 has a Non-SPDX License. You can download it from GitHub.

This is the gem5 simulator.

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Support

gem5 has a low active ecosystem.

It has 8 star(s) with 2 fork(s). There are 1 watchers for this library.

It had no major release in the last 6 months.

gem5 has no issues reported. There are no pull requests.

It has a neutral sentiment in the developer community.

The latest version of gem5 is current.

Quality

gem5 has no bugs reported.

Security

gem5 has no vulnerabilities reported, and its dependent libraries have no vulnerabilities reported.

License

gem5 has a Non-SPDX License.

Non-SPDX licenses can be open source with a non SPDX compliant license, or non open source licenses, and you need to review them closely before use.

Reuse

gem5 releases are not available. You will need to build from source code and install.

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gem5 Key Features

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gem5 Examples and Code Snippets

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Community Discussions

Trending Discussions on gem5

Using a Skewed Associative Cache in Gem5

How to assign command line argument parameters to programs run by gem5 in syscall emulation?

Full system simulation at Gem5, RISC-V

How to design a debug function similar to gem5 in C language?

rerunning the same command with different parameters

getting build error while building gem5 with riscV

Using perf_event with the ARM PMU inside gem5

How to output the data in the cache set when the cache is replaced？

Why adding a DPRINTF(XXX debug flag fails with "error:'XXX' was not declared in this scope" in gem5?

Gem5 ARM FS - Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(8,1)

QUESTION

Using a Skewed Associative Cache in Gem5

Asked 2021-Apr-06 at 16:54

I am trying to learn how to implement an L2 cache with a skewed associativity. I see there is already implemented classes for skewed associativity (skewed_associative.cc/hh) under /gem5/src/mem/cache/tags/indexing_policies/ and i would like to use this to start off with.

What I do not understand is how to access those files and specify a given cache to act as a skewed associative. Do I need to create an entire new cache class that inherits from the basecache? Or is there a way to do it through implementing a new tag?

I'm still trying to figure out how gem5 has anything structured/works, so any amount of help or links would be greatly appreciated.

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ANSWER

Answered 2021-Apr-06 at 16:54

The above comments helped lead to a solution.

When instantiating a given cache, assign its tags' indexing_policy as SkewedAssociative()

in configs/common/CacheConfig.py:

Instead of having:

Source https://stackoverflow.com/questions/66896156

QUESTION

How to assign command line argument parameters to programs run by gem5 in syscall emulation?

Asked 2021-Mar-12 at 09:13

The programs run with gem5 before are all without parameters. But what should I do if the program I am running requires parameters. I tried --cmd="add 3 4"， which is not work. I am currently trying to run Coremark with gem5. The command to run Coremark directly is ./coremark.exe 0x0 0x0 0x66 0 7 1 2000> ./run1.log.

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ANSWER

Answered 2021-Mar-12 at 09:12

You can pass command line parameters with --options as in:

Source https://stackoverflow.com/questions/66593440

QUESTION

Full system simulation at Gem5, RISC-V

Asked 2021-Feb-16 at 15:25

I want to run a 64-bit RISC-V binary without OS in gem5’s fs mode. I tried --kernel= but it didn’t stop.

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ANSWER

Answered 2021-Feb-16 at 15:25

This will be a feature in the upcoming 21.0 release. See this Jira issue for the current status: https://gem5.atlassian.net/browse/GEM5-367.

Source https://stackoverflow.com/questions/66209491

QUESTION

How to design a debug function similar to gem5 in C language?

Asked 2020-Dec-20 at 04:23

The debug information in gem5 is really amazing. You only need to use DPRINTF(FLAGA,"%d",value); where you want to output debug information.

If you add --debug-flag=FLAGA when compiling. DPRINTF(FLAGA,"%d",value)； will become printf("%d", value); otherwise it will become empty.

This is achieved through conditional compilation. But I don't know how to compile according to FLAG as above. What I think of is this:

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ANSWER

Answered 2020-Dec-20 at 04:21

I don't know if I understand. But I guess you want this:

Header file:

Source https://stackoverflow.com/questions/65376716

QUESTION

rerunning the same command with different parameters

Asked 2020-Dec-17 at 13:00

hello I'm a beginner for linux. This is the command I want to run with different parameters:

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ANSWER

Answered 2020-Dec-14 at 08:20

Humm... How do you think Python can devise what you have in mind?

In your cmd = ... statement there's no substitution.

If Your Python is recent enough (3.5+) you can use a very similar line:

Source https://stackoverflow.com/questions/65341230

QUESTION

getting build error while building gem5 with riscV

Asked 2020-Dec-09 at 09:15

So I was trying to set up gem5 with the RISC-V with the following command:

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ANSWER

Answered 2020-Dec-09 at 09:15

So my dear friends, I got the solution, but the problem itself was really hard the occur in first place, in order to problem to occur, you shouldn't be cloning the repo from the link I gave in the problem. I think the repo has some unfinished parts, so you should clone the repo from official gem5 cite, and you should be fine I suppose!

Source https://stackoverflow.com/questions/62762006

QUESTION

Using perf_event with the ARM PMU inside gem5

Asked 2020-Nov-29 at 08:29

I know that the ARM PMU is partially implemented, thanks to the gem5 source code and some publications.

I have a binary which uses perf_event to access the PMU on a Linux-based OS, under an ARM processor. Could it use perf_event inside a gem5 full-system simulation with a Linux kernel, under the ARM ISA?

So far, I haven't found the right way to do it. If someone knows, I will be very grateful!

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ANSWER

Answered 2020-Nov-18 at 14:41

Context

I was not able to use the Performance Monitoring Unit (PMU) because of a gem5's unimplemented feature. The reference on the mailing list can be found here. After a personal patch, the PMU is accessible through perf_event. Fortunately, a similar patch will be released in the official gem5 release soon, could be seen here. The patch will be described in another answer, due to the number of link limitation inside one message.

How to use the PMU C source code

This is a minimal working example of a C source code using perf_event, used to count the number of mispredicted branches by the branch predictor unit during a specific task:

Source https://stackoverflow.com/questions/63988672

QUESTION

How to output the data in the cache set when the cache is replaced？

Asked 2020-Nov-23 at 11:12

I want to learn more about the cache replacement algorithm. For example, I want to know when the cache is replaced, what data is replaced, and what data is brought to the cache. It is a good choice to output this information using the debug flag in gem5. I use classic cache. I created a debug flag to output this information. But I found that when performing the replacement algorithm, it is easy to output the data in which set and way, but it is difficult to output the data in the cacheline. Because I found that only valid, invalid, set, way information is recorded in the replacement algorithm.

I later found uint8_t *data in gem5/src/mem/cache/cache_blk.hh. This should be cache block data, but why is there only one byte, isn't a cachline 64 bytes?
What I don't understand is that when replacing, it will first find the set where the data is located according to the address. Then look for a cacheline based on the replacement algorithm. But I found that the getPossibleEntries function of the gem5/src/mem/cache/tags/indexing_policies/set_associative.cc file, return sets[extractSet(addr)]; sometimes returns four addresses, sometimes 8 are returned. Shouldn't it always return every cacheline of the cache set where the address is located? That is 8 addresses?

By the way, I use the DerivO3CPU Thanks for all related answers.

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ANSWER

Answered 2020-Nov-23 at 11:12

As a general note, there is a debug flag called CacheRepl. You may want to print whatever information you need from replacements using it.

1 - The data pointer is a pointer to the first byte of the data. It is not a string; it does not have a null marker at the end. This means that you cannot %s it right off the bat; you need to iterate through every byte using the blkSize (cache line size) to print it with %x (e.g., for (int i = 0; i < blkSize; i++) printf("%x ", blk->data[i])).

The following question can help if you want to print it as a string: Convert C++ byte array to a C string

2 - When you print anything in the Replacement Policy (RP), every object that uses that given RP will print. This includes prefetchers, buffers, tags, etc.

I don't know what is your system configuration, but you probably have at least two different tables that use the RandomRP: at least one with a 4-way associativity, and at least one with a 8-way associativity. When there are four addresses, these are the candidates for the 4-way associative table. When there are 8, it is the 8-way associative.

If, for example, you want to study the replacement information of the L2 cache, and you know that it is the only table that is 8-way associative, then you can just ignore the results that only have four addresses, since they'd refer to the replacement of other tables.

Source https://stackoverflow.com/questions/64954075

QUESTION

Why adding a DPRINTF(XXX debug flag fails with "error:'XXX' was not declared in this scope" in gem5?

Asked 2020-Nov-22 at 20:13

I want to know the cache information when the replacement algorithm is executed. So I made the following changes in the latest version of gem5. I added a line of DebugFlag('ReplacementInfo') command to the /home/cuiyujie/workspace/workGem5/gem5/src/mem/cache/replacement_policies/SConscript file. Then I added the header file #include "debug/ReplacementInfo.hh" in the /home/cuiyujie/workspace/workGem5/gem5/build/X86/params/RandomRP.cc file. Then I used DPRINTF(ReplacementInfo, "candidates"); command in this file. But an error occurred during compilation.

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ANSWER

Answered 2020-Nov-22 at 20:13

The second error was:

Source https://stackoverflow.com/questions/64950679

QUESTION

Gem5 ARM FS - Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(8,1)

Asked 2020-Nov-22 at 20:12

I'm trying to run my first full-system simulation in Gem5, but I got the following error

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ANSWER

Answered 2020-Nov-22 at 20:12

This answer to the question you mentioned points to: https://askubuntu.com/questions/41930/kernel-panic-not-syncing-vfs-unable-to-mount-root-fs-on-unknown-block0-0/1048477#1048477 which contains a detailed diagnosis procedure for this error.

For that and from the kernel message, we see clearly that root= kernel CLI parameter is incorrect: the default sda1 was used instead of the required sda.

On fs.py, the correct root= can be set with:

Source https://stackoverflow.com/questions/64957317

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