verilator

by grg C++ Version: Current License: LGPL-3.0

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kandi X-RAY | verilator Summary

verilator is a C++ library. verilator has no bugs, it has no vulnerabilities, it has a Weak Copyleft License and it has low support. You can download it from GitHub.

verilator

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verilator has a low active ecosystem.

It has 14 star(s) with 10 fork(s). There are 6 watchers for this library.

It had no major release in the last 6 months.

verilator has no issues reported. There are no pull requests.

It has a neutral sentiment in the developer community.

The latest version of verilator is current.

Quality

verilator has no bugs reported.

Security

verilator has no vulnerabilities reported, and its dependent libraries have no vulnerabilities reported.

License

verilator is licensed under the LGPL-3.0 License. This license is Weak Copyleft.

Weak Copyleft licenses have some restrictions, but you can use them in commercial projects.

Reuse

verilator releases are not available. You will need to build from source code and install.

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verilator Key Features

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Community Discussions

Trending Discussions on verilator

Verilog - bitstream works on hardware but simulation doesn't compile

Multithreaded simulation orders of magnitude slower than single-threaded

Is this caused by insufficient memory?

SyncReadMem generated verilog vs. Rocketchip emitted verilog

PyGears TypeMatchError: [0], Incomplete type: Tuple[Fixp[32], Fixp[32]]

Building Verilator (C++) with CMake built-in NDK

How to know which simulator is used in cocotb testbench?

PyGears is not generating output HDL files

How do I use the output of a program from an earlier part of a Stack/Cabal build as source in a later part of the same build?

How to use this built-in shiftRegister from Chisel3.util properly?

QUESTION

Verilog - bitstream works on hardware but simulation doesn't compile

Asked 2021-May-07 at 13:12

I am using Verilog to set up FPGA so that it blinks an LED once per second. And this is one way to do it:

...

ANSWER

Answered 2021-May-07 at 13:12

As your error message states, it is illegal to make a procedural assignment to a wire. A procedural assignment is an assignment made inside an always block, for example. You declared o_led as a wire, but then you assigned to it in an always block. You should use a reg type inside an always block. Refer to IEEE Std 1800-2017, section 10.4 Procedural assignments.

Change:

Source https://stackoverflow.com/questions/67434552

QUESTION

Multithreaded simulation orders of magnitude slower than single-threaded

Asked 2021-May-01 at 12:44

I'm using Verilator to simulate a circuit from a very simple program that just repeatedly sets the clock line high, and then low, until some output conditions are met:

...

ANSWER

Answered 2021-May-01 at 12:44

According to the devs they gave this answer:

Multithreading will only show speedups on much larger designs. In small designs the communication between cores will be much larger than leaving it on one core.

So it seems that the initial guesses were correct, and the code in question is not sufficient to exhibit a speedup. The overhead involved is to high so that it doesn't benefit from multithreading.

Source https://stackoverflow.com/questions/67335512

QUESTION

Is this caused by insufficient memory?

Asked 2021-Mar-19 at 22:17

This problem occurred when I used chipyard to compile Boom. Is this because of insufficient memory? I am running on a 1 core 2G cloud server.

/bin/bash: line 1: 9986 Killed java -Xmx8G -Xss8M -XX:MaxPermSize=256M -jar /home/cuiyujie/workspace/Boom/chipyard/generators/rocket-chip/sbt-launch.jar -Dsbt.sourcemode=true -Dsbt.workspace=/home/cuiyujie/workspace/Boom/chipyard/tools ";project utilities; runMain utilities.GenerateSimFiles -td /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig -sim verilator" /home/cuiyujie/workspace/Boom/chipyard/common.mk:86: recipe for target '/home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/sim_files.f' failed make: *** [/home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/sim_files.f] Error 137

When I adjusted the memory to 4G, this appeared.

Done elaborating. OpenJDK 64-Bit Server VM warning: INFO: os::commit_memory(0x00000006dc3b7000, 97148928, 0) failed; error='Cannot allocate memory' (errno=12)

There is insufficient memory for the Java Runtime Environment to continue. Native memory allocation (mmap) failed to map 97148928 bytes for committing reserved memory. An error report file with more information is saved as: /home/cuiyujie/workspace/Boom/chipyard/hs_err_pid2876.log /home/cuiyujie/workspace/Boom/chipyard/common.mk:97: recipe for target 'generator_temp' failed make: *** [generator_temp] Error 1

Should I adjust to 8G memory, or through what command to increase the memory size that the process can use?

When I adjusted the memory to 16G, this appeared.

/bin/bash: line 1: 2642 Killed java -Xmx8G -Xss8M -XX:MaxPermSize=256M -jar /home/cuiyujie/workspace/Boom/chipyard/generators/rocket-chip/sbt-launch.jar -Dsbt.sourcemode=true -Dsbt.workspace=/home/cuiyujie/workspace/Boom/chipyard/tools ";project tapeout; runMain barstools.tapeout.transforms.GenerateTopAndHarness -o /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.top.v -tho /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.harness.v -i /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.fir --syn-top ChipTop --harness-top TestHarness -faf /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.anno.json -tsaof /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.top.anno.json -tdf /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/firrtl_black_box_resource_files.top.f -tsf /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.top.fir -thaof /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.harness.anno.json -hdf /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/firrtl_black_box_resource_files.harness.f -thf /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.harness.fir --infer-rw --repl-seq-mem -c:TestHarness:-o:/home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.top.mems.conf -thconf /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.harness.mems.conf -td /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig -ll error" /home/cuiyujie/workspace/Boom/chipyard/common.mk:123: recipe for target 'firrtl_temp' failed make: *** [firrtl_temp] Error 137

...

ANSWER

Answered 2021-Mar-09 at 03:23

Short anwer : yes

Error 137 is thrown when your host runs out of memory.

"I am running on a 1 core 2G cloud server"

When you try to assign 8GB to the JVM, OOM-Killer says "no-no, f... no way", and kicks in sending a SIGKILL; This Killer is a proactive process that jumps in to save the system when its memory level goes too low, by killing the resource-abusive processes.

In this case, the abusive process (very abusive, indeed) is your java program, which is trying to allocate more than(*) 4 times the maximum avaliable memory in your host.

Exit Codes With Special Meanings

Source https://stackoverflow.com/questions/66539759

QUESTION

SyncReadMem generated verilog vs. Rocketchip emitted verilog

Asked 2021-Feb-24 at 17:59

I am using SyncReadMem() for sram behavioral simulation. With the generated Verilog by verilator, I hope to replace it with a commercial sram compiler compiled verilog such that I can do synthesis for the whole design including sram.

However, I noticed that the verilog emitted by SyncReadMem() is not with uniform IOs just like the sram emitted in rocketchip. I wonder how do we generate some sram verilog just like the rocketchip one, using chisel mem API like SyncReadMem()?

...

ANSWER

Answered 2021-Feb-24 at 17:59

You can use the Scala FIRRTL Compiler's "Replace Sequential Memories" pass to blackbox the memories. This is exactly what is happening with Rocket Chip.

Note that this is limited to only work if the memories have a single read port and a single write port and with read latency 1 and write latency 1.

As an example, consider the following 1r1w (one read, one write) SyncReadMem:

Source https://stackoverflow.com/questions/66344890

QUESTION

PyGears TypeMatchError: [0], Incomplete type: Tuple[Fixp[32], Fixp[32]]

Asked 2020-Nov-04 at 12:17

I have a problem while working on simple module in PyGears. I would like to make simple add operation and after that to do rounding and saturation. Error I'm getting is:

File "/home/stefan/Test/test.py", line 15, in drv(t=Tuple[Fixp[32], Fixp[32]], seq=[Tuple[3,2]]) \ TypeMatchError: [0], Incomplete type: Tuple[Fixp[32], Fixp[32]]

when resolving return type "t"

when instantiating "drv"

My code is below:

...

ANSWER

Answered 2020-Nov-04 at 12:17

I see three problems here:

First problem is that you defined Fixp incorrectly. You should also mention how many bits you want for integer part. Therefore you should define it as Fixp[10,32]
Output after add operation is in Q11.33 format, thus removing 22 bits by round operation doesn't make sense. If you would like to keep all 22 fractional bits then remove qround and leave saturate as it is. But I would suggest to do rounding to 21 bit and do saturate to saturate(11,32)
You don't need cosim

Having all this in mind working code should looks something like this

Source https://stackoverflow.com/questions/64678618

QUESTION

Building Verilator (C++) with CMake built-in NDK

Asked 2020-Sep-29 at 21:23

I tried with this example, but nothing happens:

...

ANSWER

Answered 2020-Aug-27 at 00:31

Setting all of these variables (such as CMAKE_SYSTEM_NAME, CMAKE_SYSTEM_VERSION, CMAKE_ANDROID_ARCH_ABI, etc.) should happen in the toolchain file. You may certainly experience some nasty CMake behavior by putting these in the CMakeLists.txt file itself. There is even a sample toolchain file in the CMake documentation you linked here.

Also, the CMAKE_TOOLCHAIN_FILE variable should be set on the command line when you call cmake, not in the CMake file itself. This reduces your CMakeLists.txt file to something like this:

Source https://stackoverflow.com/questions/63607389

QUESTION

How to know which simulator is used in cocotb testbench?

Asked 2020-Jul-31 at 06:39

To test my Verilog design I'm using two differents simulators : Icarus and Verilator. It's work, but there are some variations between them.

For example, I can't read module parameter with verilator, but Icarus works.

Is there a way to know which simulator is in use in python testfile ?

I would like to write something like that :

...

ANSWER

Answered 2020-Jul-31 at 06:39

The running simulator name (as a string) can be determined using cocotb.SIM_NAME. If cocotb was not loaded from a simulator, it returns None.

Source https://stackoverflow.com/questions/63186326

QUESTION

PyGears is not generating output HDL files

Asked 2020-Jul-26 at 06:20

This is the code I run, and it's not generating output HDL files:

...

ANSWER

Answered 2020-Jul-26 at 06:20

PyGears will only generate HDL files when necessary for the simulation or when directly instructed to do so via hdlgen() function (see an example below). In your case you did specify that the gain module should be simulated using Verilator HDL simulator, but you never called the simulator to execute. In other words, you need to call the sim() function at the end of your script, which you should import like this: from pygears import sim

However, when PyGears is not given a folder where to store the files, it will automatically create one inside the Temporary folder of your OS (/tmp for Ubuntu). In order to generate files local to the script, you should specify it via resdir argument of the sim() function:

Source https://stackoverflow.com/questions/63061927

QUESTION

How do I use the output of a program from an earlier part of a Stack/Cabal build as source in a later part of the same build?

Asked 2020-May-05 at 07:39

I have a very peculiar dependency situation that I would like to package up in a single Stack/Cabal package: I need to build and run my program to get the input to a code-generator which produces output that needs to be linked in to... my program.

OK so in more concrete terms, here are the steps manually:

stack build to install all dependencies, and build all non-Verilator-using executables.
stack exec phase1 to run the first phase which generates, among other things, a Verilog file and a Clash .manifest file.
I have a custom source generator, which consumes the .manifest file from step 2, and produces C++ code and a Makefile that can be used to drive Verilator.
Run the Makefile generated in step 3:
1. It runs Verilator on the Verilog sources from step 2, which produces more C++ source code and a new Makefile
2. Then it runs the newly generated second Makefile, which produces a binary library
stack build --flag phase2 builds the second executable. This executable includes .hsc files that process headers produced in step 2, and it links to the C++ libraries produced in step 4/2.

I would like to automate this so that I can just run stack build and all this would happen behind the scenes. Where do I even start?!

To illustrate the whole process, here is a self-contained model:

package.yaml ...

ANSWER

Answered 2020-May-05 at 07:39

The yak is fully bare: I managed to solve it with a custom Setup.hs.

In buildHook, I basically do whatever phase1 was supposed to do (instead of leaving it in a phase1 executable), putting all generated files in places below the buildDir of the LocalBuildInfo argument. These generated files are C++ source files and an .hsc file.
I then run make in the right directory, producing some libFoo.a.
Still in buildHook, now the fun part starts: editing the Executables in the PackageDescription.

I add the hsc file's location to hsSourceDirs, and the module itself to otherModules. Since hsc2hs requires access to the generated C++ headers, I also add the right directory to includeDirs. For the library itself, I add to extraLibDirs and edit options to link statically to libFoo.a, by passing flags directly to the linker.
The result of all this is a modified set of Executables, which I put back into the PackageDescription before passing it to the default buildHook. That one then runs hsc2hs and ghc to compile and link the phase2 executables.

I have put a full example project on Github. Look at Setup.hs and clashilator/src/Clash/Clashilator/Setup.hs to see this in action; in particular, here is the editing of the Executables in the PackageDescription:

Source https://stackoverflow.com/questions/61572353

QUESTION

How to use this built-in shiftRegister from Chisel3.util properly?

Asked 2020-Apr-29 at 17:58

I tried to compare this built-in shiftRegister with some common shift registers in the chisel-tutorial. But this one seems not actually shifting the bits? https://github.com/freechipsproject/chisel3/blob/9f620e06bacc2882068adfd4972ec2e9a87ea723/src/main/scala/chisel3/util/Reg.scala#L33

...

ANSWER

Answered 2020-Apr-29 at 17:58

From your link with the ScalaDoc comment:

Source https://stackoverflow.com/questions/61494871

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Install verilator

You can download it from GitHub.

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