CMWX1ZZABZ | sketches using the Arduino core
kandi X-RAY | CMWX1ZZABZ Summary
kandi X-RAY | CMWX1ZZABZ Summary
Collection of Arduino sketches (make sure you have the latest Ardino core installed!) for various devices with embedded CMWX1ZZABZ (STM32L082 and SX1276) as host. The devices include the 18 mm x 45 mm Grasshopper development board, the 23 mm x 23 mm LoRa SensorTile, and the 23 mm x 46 mm Cricket Asset Tracker. See here for more discussion.
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CMWX1ZZABZ Key Features
CMWX1ZZABZ Examples and Code Snippets
Community Discussions
Trending Discussions on CMWX1ZZABZ
QUESTION
I'm using the B-L072Z-LRWAN1 with the CMWX1ZZABZ-091 LoRa® /Sigfox™ module (Murata)
The internal RTC (real time clock) is inaccurate and I'm seeing 10 seconds loss per day for some modules.
My question is, why could this be? Datasheet says 1.73 seconds / 20ppm for the LSE. The TXCO is 2ppm. How can I calibrate the RTC using TXCO?
I know there is also temperature that influences the accuracy but I think that is in an insignificant range i.e. does not explain 10seconds /day.
...ANSWER
Answered 2018-Jul-25 at 11:51(false statement about LSE removed)
How can I calibrate the RTC using TXCO?
TXCO can supply HSE, and you can derive the RTC clock from HSE through a series of prescalers.
Section 8.5 in the User Manual says,
When an accurate external-high-speed clock is needed by the STM32, the TCXO_OUT clock pin is supplied by the module pin PH0_OSC_IN by closing SB13.
First, close SB13 with a drop of tin.
PH0_OSC_IN is the HSE bypass clock source. Set HSEBYP
then HSEON
in RCC->CR
to have an accurate 32 MHz HSE clock. But wait, first you have to set RTCPRE
to 3
in order to prescale it by 16 for the RTC module. Select this as the RTC clock in RCC->CSR
.
Now the RCC generates a 2 MHz clock for the RTC (fRTCCLK = 2000000). You scale it further down to 1 Hz (fCK_SPRE = 1) with the RTC->PRER
register. It has two bitfields, PREDIV_A
can go from 0
to 127
, PREDIV_S
from 0
to 32767
. Solving the integer equation
fCK_SPRE = fRTCCLK / ((PREDIV_S + 1) × (PREDIV_A + 1))
with the above constraints gives
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