fpga-booleanring-bfs | Hybrid BFS on Xilinx Zynq

fpga-booleanring-bfs is a C++ library. fpga-booleanring-bfs has no bugs, it has no vulnerabilities and it has low support. You can download it from GitHub.

The "gist" of the hybrid method is to take advantage of the varying amount of parallelism (due to exponential growth and decay of frontier size) during breadth-first search on a small-world network: (very) few nodes are visited during the first and last few steps, and not much parallelism is available, so these steps are carried out on the CPU. The middle steps visit many more nodes and have greater parallelism, and hence are explored on a high-throughput FPGA accelerator. Since the Zynq offers both Cortex-A9 CPU cores and FPGA fabric on the same chip (and sharing the same DRAM), there is little penalty associated with switching execution modes. The hardware accelerator itself comes in two flavors (called "dense frontier" and "sparse frontier"), which perform the exact same function but in different ways. The sparse frontier version is quite similar to traditional BFS with current/next queues, adding only unvisited nodes to the next queue. The dense frontier version visits all nodes and edges in the graph at every BFS step. Although this may sound quite wasteful, it has a much simpler DRAM access pattern and can utilize most of the available DRAM bandwidth, which actually outperforms the sparse version (see paper for more details).