verilator | Verilator open-source SystemVerilog simulator | Compiler library

by verilator C++ Version: v5.010 License: LGPL-3.0

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kandi X-RAY | verilator Summary

verilator is a C++ library typically used in Utilities, Compiler applications. verilator has no bugs, it has no vulnerabilities, it has a Weak Copyleft License and it has medium support. You can download it from GitHub.

Verilator open-source SystemVerilog simulator and lint system

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verilator has a medium active ecosystem.

It has 1640 star(s) with 433 fork(s). There are 76 watchers for this library.

It had no major release in the last 6 months.

There are 249 open issues and 2568 have been closed. On average issues are closed in 395 days. There are 19 open pull requests and 0 closed requests.

It has a neutral sentiment in the developer community.

The latest version of verilator is v5.010

Quality

verilator has 0 bugs and 0 code smells.

Security

verilator has no vulnerabilities reported, and its dependent libraries have no vulnerabilities reported.

verilator code analysis shows 0 unresolved vulnerabilities.

There are 0 security hotspots that need review.

License

verilator is licensed under the LGPL-3.0 License. This license is Weak Copyleft.

Weak Copyleft licenses have some restrictions, but you can use them in commercial projects.

Reuse

verilator releases are not available. You will need to build from source code and install.

It has 626 lines of code, 48 functions and 3 files.

It has high code complexity. Code complexity directly impacts maintainability of the code.

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verilator Key Features

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Community Discussions

Trending Discussions on verilator

Timescale missing on the module as other modules have it Verilator error

How to trace specific signals using Verilator?

SystemVerilog Dataflow Modeling Ripple-Adder with array instances

Verilator, running simulator gives: Invalid argument

Verilog - bitstream works on hardware but simulation doesn't compile

Multithreaded simulation orders of magnitude slower than single-threaded

Is this caused by insufficient memory?

SyncReadMem generated verilog vs. Rocketchip emitted verilog

PyGears TypeMatchError: [0], Incomplete type: Tuple[Fixp[32], Fixp[32]]

Building Verilator (C++) with CMake built-in NDK

QUESTION

Timescale missing on the module as other modules have it Verilator error

Asked 2022-Mar-25 at 19:53

I am trying to add an accelerator to the rocket chip framework through the MMIO peripheral. I went through the GCD example and was able to build the basic GCD code. I then replaced the GCD with an accelerator which has it's own Config, Parameters and Field information. Now when I try to pass this information to the rocket chip there is a name clash with the freechips.rocketchip.config.{Parameters, Field, Config}. I tried specifying the whole path i.e; accelerator.util.conig.Parameters to distinguish it from freechips.rocketchip.config.Parameters but it still gave me the same error. When I remove my accelerator configs and parameters and pass simple hand made parameters the build is successful, however, when I add my config I get %Error-TIMESCALEMOD and this error is in the generated file which I am not modifying. I tried a work around by altering my verilator options but that goes down a rabbit hole of errors. I have narrowed down the problem to the fact that this is being caused because I am using two different configs both of which have their own Config.scala file shown here Is there a way to fix this problem? I have attached the error with this question.

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ANSWER

Answered 2022-Mar-25 at 19:53

The problem was with a blackbox, not sure why it was giving me that error, but yes we can mix two different configs having different util.config files. We just have to specify them explicitly.

Source https://stackoverflow.com/questions/71534660

QUESTION

How to trace specific signals using Verilator?

Asked 2022-Feb-11 at 13:45

I have a system which I want to trace with Verilator, but using a VCD trace file is highly resource-demanding (hundreds of gigabytes) and time consuming. I changed the trace file type to FST, and the file size is reasonable, but it is still time-consuming. Tracing the whole system is not my goal at the moment because I only want the values of 8 signals, not the 16000 signals of the system.

How can I trace specific signals using Verilator?

Any help or hint would be much appreciated.

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ANSWER

Answered 2022-Feb-11 at 13:45

The Verilator manual has a FAQ for this: How do I speed up writing large waveform (trace) files?

These are the suggestions (briefly):

Delay calling open
Add the /*verilator tracing_off*/ metacomment
Use the --trace-depth 1 option
FST (which you already tried)
Write your trace files to a local solid-state drive, instead of to a network drive

Source https://stackoverflow.com/questions/71049225

QUESTION

SystemVerilog Dataflow Modeling Ripple-Adder with array instances

Asked 2021-Dec-12 at 08:59

I've implemented a (working) ripple-carry adder using generation to create 16 different full_adder instances (the full_adder works as intended):

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ANSWER

Answered 2021-Dec-03 at 12:25

Array of instances in verilog is a type of a generate block and instantiates a module several times, adding array index to its name and doing some job with ports. Array of instances are usually not well understood and seldom used in behavioral verilog.

Since it is a generate block, you cannot use ranges on array instances. 'adders[15:1]' is illegal. You need to use a generate loop to access them instance by instance. Also 'assign adders[15:1].cin' represents a connection to an internal signal of the submodule instance, not to its input port. So, the compiler is absolutely correct.

You left unconnected ports of the module instances and trying to access their internal signals. It is a bad practice in the first place. To fix it you should figure out how to use port connections instead. An extra code will be needed to reassign vector to satisfy your algorithm, at least around 'carries'.

Source https://stackoverflow.com/questions/70210106

QUESTION

Verilator, running simulator gives: Invalid argument

Asked 2021-Nov-04 at 22:53

I'm following this tutorial. On page 24 I don't get the Makefile the tutorial talks about. When I run ./thruwire it says: bash: ./thruwire: Invalid argument.

This is my thruwire.v:

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ANSWER

Answered 2021-Nov-04 at 22:53

My toolbox was broken. A working toolbox does not give these errors as has been discussed in the comments (unfortunately the user deleted them). I guess trying to build the whole toolsuite yourself is not a good idea unless you really know what you are doing. I found a cad suite that can be readily used without problems. It has all the needed tools precompiled and working.

Source https://stackoverflow.com/questions/69838684

QUESTION

Verilog - bitstream works on hardware but simulation doesn't compile

Asked 2021-May-07 at 13:12

I am using Verilog to set up FPGA so that it blinks an LED once per second. And this is one way to do it:

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ANSWER

Answered 2021-May-07 at 13:12

As your error message states, it is illegal to make a procedural assignment to a wire. A procedural assignment is an assignment made inside an always block, for example. You declared o_led as a wire, but then you assigned to it in an always block. You should use a reg type inside an always block. Refer to IEEE Std 1800-2017, section 10.4 Procedural assignments.

Change:

Source https://stackoverflow.com/questions/67434552

QUESTION

Multithreaded simulation orders of magnitude slower than single-threaded

Asked 2021-May-01 at 12:44

I'm using Verilator to simulate a circuit from a very simple program that just repeatedly sets the clock line high, and then low, until some output conditions are met:

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ANSWER

Answered 2021-May-01 at 12:44

According to the devs they gave this answer:

Multithreading will only show speedups on much larger designs. In small designs the communication between cores will be much larger than leaving it on one core.

So it seems that the initial guesses were correct, and the code in question is not sufficient to exhibit a speedup. The overhead involved is to high so that it doesn't benefit from multithreading.

Source https://stackoverflow.com/questions/67335512

QUESTION

Is this caused by insufficient memory?

Asked 2021-Mar-19 at 22:17

This problem occurred when I used chipyard to compile Boom. Is this because of insufficient memory? I am running on a 1 core 2G cloud server.

/bin/bash: line 1: 9986 Killed java -Xmx8G -Xss8M -XX:MaxPermSize=256M -jar /home/cuiyujie/workspace/Boom/chipyard/generators/rocket-chip/sbt-launch.jar -Dsbt.sourcemode=true -Dsbt.workspace=/home/cuiyujie/workspace/Boom/chipyard/tools ";project utilities; runMain utilities.GenerateSimFiles -td /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig -sim verilator" /home/cuiyujie/workspace/Boom/chipyard/common.mk:86: recipe for target '/home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/sim_files.f' failed make: *** [/home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/sim_files.f] Error 137

When I adjusted the memory to 4G, this appeared.

Done elaborating. OpenJDK 64-Bit Server VM warning: INFO: os::commit_memory(0x00000006dc3b7000, 97148928, 0) failed; error='Cannot allocate memory' (errno=12)

There is insufficient memory for the Java Runtime Environment to continue. Native memory allocation (mmap) failed to map 97148928 bytes for committing reserved memory. An error report file with more information is saved as: /home/cuiyujie/workspace/Boom/chipyard/hs_err_pid2876.log /home/cuiyujie/workspace/Boom/chipyard/common.mk:97: recipe for target 'generator_temp' failed make: *** [generator_temp] Error 1

Should I adjust to 8G memory, or through what command to increase the memory size that the process can use?

When I adjusted the memory to 16G, this appeared.

/bin/bash: line 1: 2642 Killed java -Xmx8G -Xss8M -XX:MaxPermSize=256M -jar /home/cuiyujie/workspace/Boom/chipyard/generators/rocket-chip/sbt-launch.jar -Dsbt.sourcemode=true -Dsbt.workspace=/home/cuiyujie/workspace/Boom/chipyard/tools ";project tapeout; runMain barstools.tapeout.transforms.GenerateTopAndHarness -o /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.top.v -tho /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.harness.v -i /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.fir --syn-top ChipTop --harness-top TestHarness -faf /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.anno.json -tsaof /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.top.anno.json -tdf /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/firrtl_black_box_resource_files.top.f -tsf /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.top.fir -thaof /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.harness.anno.json -hdf /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/firrtl_black_box_resource_files.harness.f -thf /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.harness.fir --infer-rw --repl-seq-mem -c:TestHarness:-o:/home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.top.mems.conf -thconf /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.harness.mems.conf -td /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig -ll error" /home/cuiyujie/workspace/Boom/chipyard/common.mk:123: recipe for target 'firrtl_temp' failed make: *** [firrtl_temp] Error 137

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ANSWER

Answered 2021-Mar-09 at 03:23

Short anwer : yes

Error 137 is thrown when your host runs out of memory.

"I am running on a 1 core 2G cloud server"

When you try to assign 8GB to the JVM, OOM-Killer says "no-no, f... no way", and kicks in sending a SIGKILL; This Killer is a proactive process that jumps in to save the system when its memory level goes too low, by killing the resource-abusive processes.

In this case, the abusive process (very abusive, indeed) is your java program, which is trying to allocate more than(*) 4 times the maximum avaliable memory in your host.

Exit Codes With Special Meanings

Source https://stackoverflow.com/questions/66539759

QUESTION

SyncReadMem generated verilog vs. Rocketchip emitted verilog

Asked 2021-Feb-24 at 17:59

I am using SyncReadMem() for sram behavioral simulation. With the generated Verilog by verilator, I hope to replace it with a commercial sram compiler compiled verilog such that I can do synthesis for the whole design including sram.

However, I noticed that the verilog emitted by SyncReadMem() is not with uniform IOs just like the sram emitted in rocketchip. I wonder how do we generate some sram verilog just like the rocketchip one, using chisel mem API like SyncReadMem()?

...

ANSWER

Answered 2021-Feb-24 at 17:59

You can use the Scala FIRRTL Compiler's "Replace Sequential Memories" pass to blackbox the memories. This is exactly what is happening with Rocket Chip.

Note that this is limited to only work if the memories have a single read port and a single write port and with read latency 1 and write latency 1.

As an example, consider the following 1r1w (one read, one write) SyncReadMem:

Source https://stackoverflow.com/questions/66344890

QUESTION

PyGears TypeMatchError: [0], Incomplete type: Tuple[Fixp[32], Fixp[32]]

Asked 2020-Nov-04 at 12:17

I have a problem while working on simple module in PyGears. I would like to make simple add operation and after that to do rounding and saturation. Error I'm getting is:

File "/home/stefan/Test/test.py", line 15, in drv(t=Tuple[Fixp[32], Fixp[32]], seq=[Tuple[3,2]]) \ TypeMatchError: [0], Incomplete type: Tuple[Fixp[32], Fixp[32]]

when resolving return type "t"

when instantiating "drv"

My code is below:

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ANSWER

Answered 2020-Nov-04 at 12:17

I see three problems here:

First problem is that you defined Fixp incorrectly. You should also mention how many bits you want for integer part. Therefore you should define it as Fixp[10,32]
Output after add operation is in Q11.33 format, thus removing 22 bits by round operation doesn't make sense. If you would like to keep all 22 fractional bits then remove qround and leave saturate as it is. But I would suggest to do rounding to 21 bit and do saturate to saturate(11,32)
You don't need cosim

Having all this in mind working code should looks something like this

Source https://stackoverflow.com/questions/64678618

QUESTION

Building Verilator (C++) with CMake built-in NDK

Asked 2020-Sep-29 at 21:23

I tried with this example, but nothing happens:

...

ANSWER

Answered 2020-Aug-27 at 00:31

Setting all of these variables (such as CMAKE_SYSTEM_NAME, CMAKE_SYSTEM_VERSION, CMAKE_ANDROID_ARCH_ABI, etc.) should happen in the toolchain file. You may certainly experience some nasty CMake behavior by putting these in the CMakeLists.txt file itself. There is even a sample toolchain file in the CMake documentation you linked here.

Also, the CMAKE_TOOLCHAIN_FILE variable should be set on the command line when you call cmake, not in the CMake file itself. This reduces your CMakeLists.txt file to something like this:

Source https://stackoverflow.com/questions/63607389

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Vulnerabilities

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Install verilator

You can download it from GitHub.

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