riscv | RISC-V processor model

 by   ArchC C Version: Current License: No License

kandi X-RAY | riscv Summary

kandi X-RAY | riscv Summary

riscv is a C library. riscv has no bugs, it has no vulnerabilities and it has low support. You can download it from GitHub.

RISC-V processor model
Support
    Quality
      Security
        License
          Reuse

            kandi-support Support

              riscv has a low active ecosystem.
              It has 5 star(s) with 8 fork(s). There are 6 watchers for this library.
              OutlinedDot
              It had no major release in the last 6 months.
              There are 1 open issues and 0 have been closed. There are no pull requests.
              It has a neutral sentiment in the developer community.
              The latest version of riscv is current.

            kandi-Quality Quality

              riscv has no bugs reported.

            kandi-Security Security

              riscv has no vulnerabilities reported, and its dependent libraries have no vulnerabilities reported.

            kandi-License License

              riscv does not have a standard license declared.
              Check the repository for any license declaration and review the terms closely.
              OutlinedDot
              Without a license, all rights are reserved, and you cannot use the library in your applications.

            kandi-Reuse Reuse

              riscv releases are not available. You will need to build from source code and install.
              Installation instructions, examples and code snippets are available.

            Top functions reviewed by kandi - BETA

            kandi's functional review helps you automatically verify the functionalities of the libraries and avoid rework.
            Currently covering the most popular Java, JavaScript and Python libraries. See a Sample of riscv
            Get all kandi verified functions for this library.

            riscv Key Features

            No Key Features are available at this moment for riscv.

            riscv Examples and Code Snippets

            No Code Snippets are available at this moment for riscv.

            Community Discussions

            QUESTION

            I can't understand this line of code in xv6
            Asked 2021-Jun-04 at 13:21

            Despite consulting the documentation, I still can't understand this line:swtch(&c->scheduler, &p->context);.

            My question: I know this line is to switch p->context, including save registers and restore registers, but I can't understand the pc change in this process, that is what execution order of this code? After theswtch(&c->scheduler, &p->context); is executed, is it immedidate to execute c->proc = 0;, then the effect of executing c->proc=p; disappears? I am confused now.

            code link: https://github.com/mit-pdos/xv6-riscv/blob/riscv/kernel/proc.c line 456

            ...

            ANSWER

            Answered 2021-Jun-04 at 13:21

            This is literally the code that was so confusing that its original authors wrote "You are not expected to understand this" in the comments, so don't feel bad for not understanding it.

            The key thing you may have missed is that p->context contains an address where swtch is to resume execution of process p. It's set up, for instance, here:

            Source https://stackoverflow.com/questions/67836212

            QUESTION

            How to cross-compile elfutils for RISC-V?
            Asked 2021-May-15 at 20:22

            I want to cross-compile elfutils for a RISC-V target and I get linker errors which I don't know how to solve. I use the riscv-gnu-toolchain.

            Build zlib

            elfutils is build against zlib, so I need to build it first:

            ...

            ANSWER

            Answered 2021-May-15 at 20:22

            I needed to add LIBS="-lz -lzstd -llzma". The full configuration command looks like this:

            Source https://stackoverflow.com/questions/67548406

            QUESTION

            How to track jumps on riscv instructions when pthreads and virtual functions are explotied?
            Asked 2021-May-11 at 02:44

            I am writing a tool for tracking jumps(JAL/JALR) instructions on riscv instructions. I am using https://github.com/illumine/disk-benchmark/blob/master/src/disk-benchmark.c disk benchmark to test my tool. The tool is tracking jumps on binary files when virtual functions and pthreads are not used but have difficulties to track when pthreads are used. Here is the objdump of binary file on riscv:

            ...

            ANSWER

            Answered 2021-May-11 at 02:44

            We can trace the jumps on binary file only if we don't have any indirect jumps and if the trace is not involved in library functions. In my case I couldn't trace since the program had a lot of pthreads and indirect jumps.

            Source https://stackoverflow.com/questions/66274188

            QUESTION

            RISC-V Linux running on Qemu
            Asked 2021-Mar-26 at 10:47

            I am trying to run RISC-V linux on Qemu, following the instruction: Running 64- and 32-bit RISC-V Linux on QEMU
            I have downloaded and installed the RISC-V GNU compiller Toolchain

            ...

            ANSWER

            Answered 2021-Mar-26 at 10:47

            This is standart problem, try to type whereis riscv64-unknown-linux-gnu-gcc if it get nothing, try to type riscv64- and press tab, you should see necessary prefix you need paste after CROSS_COMPILE=. Also maybe you also need add PATH variable with path to riscv-toolchain's bin in ~/.bashrc or/and in ~/.profile.

            Build own linux is a big task, maybe you should learn some manuals about toolchain and building linux.

            riscv toolchain link

            Source https://stackoverflow.com/questions/66805107

            QUESTION

            make qemu on xv6-riscv gets stucked at qemu-system-riscv64 ... command
            Asked 2021-Mar-20 at 06:47

            On Ubuntu 20.04, I installed the xv6 project using the page Tools Used in 6.828

            ...

            ANSWER

            Answered 2021-Mar-20 at 06:47

            This has been mentioned in Tools Used in 6.S081

            At this moment in time, it seems that the package qemu-system-misc has received an update that breaks its compatibility with our kernel. If you run make qemu and the script appears to hang after

            Source https://stackoverflow.com/questions/66390948

            QUESTION

            Is there a blank Unicode character matching emoji width?
            Asked 2021-Mar-16 at 12:38

            Does Unicode define a blank character (like "Em Space" or "En Space") with the same width as any/some emoji (something like "Emoji Space")? If yes, which one is it?

            I'd like to be able to format a fixed-width font plain-text table containing emojis (CI report e-mail). They seem to be impossible to align either with regular or any other spaces I tried (compare "x86_64", "arm" and "mips" lines):

            ...

            ANSWER

            Answered 2021-Mar-07 at 10:44

            This is basically a font issue. You'd need a monospace font with a glyph for U+2705 WHITE HEAVY CHECK MARK and the other characters, and make sure to disable Emojis with a variation selector. Web browsers typically replace missing characters with a fallback font, but then you lose control over character spacing. Your best bet is to use characters which are more likely to be supported. Unfortunately, even U+2713 CHECK MARK seems to be supported only in a few monospace fonts.

            Source https://stackoverflow.com/questions/66496671

            QUESTION

            MMU initialization on linux
            Asked 2021-Mar-15 at 08:41

            I'm writing my linux risc v emulator in rust.

            I stumble on mmu initialization.

            OpenSBI works fine, prints info and transfers control to the linux kernel. But the emulator crashes when it tries to read the next instruction after satp setup ffffffe00000008c in arch/riscv/kernel/head.S:119. (Transfer between SATP_MODE_BARE and SATP_MODE_SV39)

            Emulator memory layout:

            ...

            ANSWER

            Answered 2021-Mar-15 at 08:41

            u/stepinfusion on reddit

            If we are reading the same version of head.S, it looks to me that the instruction at ...008c is head.S:97, the first time satp is modified. head.S:119 is the ret instruction at ...00ac.

            I don't know this code very well but it looks like it's supposed to trap at head.S:97 and stvec is pointing to the next instruction's virtual address. It's an interesting way to switch from running in physical space to virtual space without an identity mapping.

            Source https://stackoverflow.com/questions/66617488

            QUESTION

            How does the Linux kernel enter supervisor mode in x86?
            Asked 2021-Mar-05 at 23:58

            I tried to probe the event when the mode switch happens (user->kernel mode), as a result, I need to find which function will be triggered when the transition happens.

            It seems that SBI is the placed doing transition for RISC-V. I'm wondering where is the code to handle this for x86?

            ...

            ANSWER

            Answered 2021-Mar-05 at 13:57

            It's not that simple. In x86, there are 4 different privilege levels: 0 (operating system kernel), 1, 2, and 3 (applications). Privilege levels 1 and 2 aren't used in Linux: the kernel runs at privilege level 0 while user space code runs at privilege level 3. The current privilege level (CPL) is stored in bits 0 and 1 of the CS (code segment) register.

            There are multiple ways in which the transition from user to kernel can happen:

            • Through hardware interrupts: page faults, general protection faults, devices, hardware timer, and so on.
            • Through software interrupts: the int instruction raises a software interrupt. The most common in Linux is int 0x80, which is configured to be used for system calls from user space to kernel space.
            • Through specialized instructions like sysenter and syscall.

            In any case, there is no actual code that does the transition: it is done by the processor itself, which switches from one privilege level to the other, and sets up segment selectors, instruction pointer, stack pointer and more according to the information that was set up by the kernel right after booting.

            In the case of interrupts, the entries of the Interrupt Descriptor Table (IDT) are used. See this useful documentation page about interrupts in Linux which explains more about the IDT. If you want to get into the details, check out Chapter 5 of the Intel 64 and IA-32 architectures software developer's manual, Volume 3.

            In short, each IDT entry specifies a descriptor privilege level (DPL) and a new code segment and offset. In case of software interrupts, some privilege level checks are made by the processor (one of which is CPL <= DPL) to determine whether the code that issued the interrupt has the privilege to do so. Then, the interrupt handler is executed, which implicitly sets the new CS register with the privilege level bits set to 0. This is how the canonical int 0x80 syscall for x86 32bit is made.

            In case of specialized instructions like sysenter and syscall, the details differ, but the concept is similar: the CPU checks privileges and then retrieves the information from dedicated Model Specific Registers (MSR) that were previously set up by the kernel after boot.

            For system calls the result is always the same: user code switches to privilege level 0 and starts executing kernel code, ending up right at the beginning of one of the different syscall entry points defined by the kernel.

            Possible syscall entry points are:

            Source https://stackoverflow.com/questions/66485051

            QUESTION

            Raspberry PI 3 UART0 Not Transmitting (Bare-Metal)
            Asked 2021-Feb-27 at 01:23

            Introduction

            I have been working on writing my own bare metal code for a Raspberry PI as I build up my bare metal skills and learn about kernel mode operations. However, due to the complexity, amount of documentation errors, and missing/scattered info, it has been extremely difficult to finally bring up a custom kernel on the Raspberry PI. However, I finally got that working.

            A very broad overview of what is happening in the bootstrap process

            My kernel loads into 0x80000, sends all cores except core 0 into an infinite loop, sets up the Stack Pointer, and calls a C function. I can setup the GPIO pins and turn them on and off. Using some additional circuitry, I can drive LEDs and confirm that my code is executing.

            The problem

            However when it comes to the UART, I have hit a wall. I am using UART0 (PL011). As far as I can tell, the UART is not outputting, although I could be missing it on my scope since I only have an analog oscilloscope. The code gets stuck when outputting the string. I have determined through hours of reflashing my SD card with different YES/NO questions to my LEDs that it is stuck in an infinite loop waiting for the UART Transmit FIFO Full flag to clear. The UART only accepts 1 byte before becoming full. I can not figure out why it is not transmitting the data out. I am also not sure if I have correctly set my baud-rate, but I don't think that would cause the TX FIFO to stay filled.

            Getting a foothold in the code

            Here is my code. The execution begins at the very beginning of the binary. It is constructed by being linked with symbol "my_entry_pt" from assembly source "entry.s" in the linker script. That is where you will find the entry code. However, you probably only need to look at the last file which is the C code in "base.c". The rest is just bootstrapping up to that. Please disregard some comments/names which don't make sense. This is a port (of primarily the build infrastructure) from an earlier bare-metal project of mine. That project used a RISC-V development board which uses a memory mapped SPI flash to store the binary code of the program.:

            [Makefile]

            ...

            ANSWER

            Answered 2021-Feb-25 at 06:27

            My suggestion:

            • flash your SD card to a rpi distribution to make sure the hardware is still working
            • if the hardware is good, check the difference of your code with the in-kernel serial driver

            Source https://stackoverflow.com/questions/66361843

            QUESTION

            Why is a header included multiple times on one architecture, but only once in another?
            Asked 2021-Feb-10 at 20:20

            I'm trying to compile a program (the splash2x.raytrace package of the PARSEC benchmark suite, after transformations) on two architectures - amd64 and riscv64; however, when I try to natively compile it on both, I get a different behavior that I can't explain.

            Specifically, while on amd64 it compiles, on riscv64 it fails with a lot of multiple definition of....

            The program has around a dozen .c files, and one header, included in all of them ("rt.h").

            A sample variable is:

            ...

            ANSWER

            Answered 2021-Feb-07 at 00:55

            The error message does not say that the header was included multiple times. It says that the same symbol exists in multiple object files and the header file is just the source of that symbol.

            If an H file defines a symbol, then in fact every C file that includes it will define that symbol because only a compiled file can define a symbol and H files are not compiled, they are included into C files when those C files are compiled (actually when they are preprocessed but that usually happens when they are compiled). And if multiple C files define the same symbol, are compiled, and linked together (note that this is a ld error, so it is a linker error), you end up with multiple symbols of the same name, which is not allowed by C standard.

            If a H file just wants to inform a C file about the existence and type of a symbol that is defined elsewhere, e.g. in another C file, it must only declare the symbol by prefixing it with extern.

            Source https://stackoverflow.com/questions/66082888

            Community Discussions, Code Snippets contain sources that include Stack Exchange Network

            Vulnerabilities

            No vulnerabilities reported

            Install riscv

            Use the official RISC-V toolchain for creating the executables. Follow the steps on the RISC-V page to download the toolchain. Use the master branch when generating the toolchain binaries.

            Support

            For any new features, suggestions and bugs create an issue on GitHub. If you have any questions check and ask questions on community page Stack Overflow .
            Find more information at:

            Find, review, and download reusable Libraries, Code Snippets, Cloud APIs from over 650 million Knowledge Items

            Find more libraries
            CLONE
          • HTTPS

            https://github.com/ArchC/riscv.git

          • CLI

            gh repo clone ArchC/riscv

          • sshUrl

            git@github.com:ArchC/riscv.git

          • Stay Updated

            Subscribe to our newsletter for trending solutions and developer bootcamps

            Agree to Sign up and Terms & Conditions

            Share this Page

            share link