Butterfly | C library that implements a very simple 'dynamic | Data Visualization library

it should

In FPGA, when designing modules that multiply and add you want those resources to synthesize as DSP blocks. The DSP blocks have a built in multiply and accumulate. In the code shown there are 4 multiplies and 4 adds, if this synthesizes as 4 DSP blocks this is the optimum result. The 'pipeline' (registers) end up built into the DSP blocks, so they are somewhat free.

This is an optimal use of resources, however the part has a finite number of DSP blocks which will limit the size of the transform.

Another limitation is the bit width; the Xilinx DSP48 block max size for multiply is 25x18. Check other vendors for different sizes.

The goal is to have the synthesis tool infer the DSP block during synthesis. Generally, best practice is to NOT instantiate a DSP block in Verilog or VHDL RTL code. There are exceptions, but start with an inference rather than instantiation workflow.

To that end, run the design thru the synthesis flow and look at the utilization. Optimally 4 DSP blocks and a small number of LUTS would be inferred by synthesis for a 4-point transform. If it does something else (example using a lot of LUTS and registers) then re-code to utilize the DSP blocks.

Each vendor has coding style recommendations with the goal of mapping to DSP blocks.

This Xilinx paper (DSP blocks used in Xilinx 7-Series) is somewhat helpful. I say somewhat because it focus on FIR, but many of the same ideas apply to FFT. https://www.xilinx.com/support/documentation/user_guides/ug479_7Series_DSP48E1.pdf

The clk->out delay (timing performance) of the DSP block is about that of a reg.
Generally, if a design meets the clock timing constraint after place & route, you are good to go to the lab ( WRT timing :) ). Some design organizations recommend/require that all module IO are registered. This may be overkill. I have found that with 7-series the designs meet timing over the years as the parts get fuller and fuller during development if the number of level of logic is about 10 or less. This is a rule of thumb not a strict brick-wall rule. With 12 levels of logic its starting to get marginal, at 15 it might be the critical path in the design.

To determine the levels of logic, open the timing analyzer, right click on the worst timing path on the clock, and 'analyze' or 'show schematic' for the path. The analysis shows the number of levels of logic. Vivado can show you a schematic view of the timing path so you can see if it spans several modules to help answer the question 'how much do I need to pipeline this module'.

It also depends on the clock rate, the device and the speed grade. If you are doing anything > 200MHz in a > 50% utilized device, then additional pipelining and keeping the combinational logic down to 2-3 levels is needed. This also is my experience and a rough guideline, not a rule or requirement. There may be FPGAs that have generous timing margins for the fabric at 400 MHz, and are relatively full; I have not seen one though.

Your hook is async so u need to wait for the next update. Here is the docs that talks more about it.

You are simply missing the clip property. That tells the object to prevent child objects from drawing outside of its borders. clip is set to false by default because most of the time its not needed and has a little bit of a performance hit.

Nullable<> is a little tricky. When you find such a property you have to check against the given entity what you get back from prop.GetValue(entity). Either this is null (and trying to call ToString() would be impossible) or you get back the value type (but boxed as an object), but you can call the normal ToString() method.

It can be a bug of that Flutter package, indeed. Have you tried to create an issue in GitHub of that package?

Secondly, during my development, I see several times when emulators just fail and real devices always work. The solution I used is - simply to do not test them on simulators. Real users never use simulators, aren't they?

It can be a bug of the library when running on x86 arch (the arch simulators use). Then, nobody with a real device (arm arch) will ever see the bug.

Thirdly, what about trying to use "cloud real devices" to test whether they work on real Pixel devices that you are worried about. There are many platforms that host some real devices and you can connect to them via a webpage and test your app.

With a dict comprehension to grab all attributes of hub.Image which are upper-case only:

The problem is in your butterfly.png & basketball.png placed wrong directory.

Just move those image drawable-v24 to drawable

You can specify the frame.colour for the ellipses and the colour for the points: