nasm | Mirror of main nasm git repo at http : //repo.or.cz/w/nasm.git
kandi X-RAY | nasm Summary
kandi X-RAY | nasm Summary
Many many developers all over the net respect NASM for what it is. Now we have good news for you: NASM is licensed under the "simplified" (2-clause) BSD license. This means its development is open to even wider society of programmers wishing to improve their lovely assembler. The NASM project is now situated at SourceForge.net, the most popular Open Source development site on the Internet. Visit our website at and our SourceForge project at See the file CHANGES for the description of changes between revisions, and the file AUTHORS for a list of contributors.
Support
Quality
Security
License
Reuse
Top functions reviewed by kandi - BETA
Currently covering the most popular Java, JavaScript and Python libraries. See a Sample of nasm
nasm Key Features
nasm Examples and Code Snippets
Community Discussions
Trending Discussions on nasm
QUESTION
I am writing a C interface for CPU's cpuid
instruction. I'm just doing this as kind of an exercise: I don't want to use compiler-depended headers such as cpuid.h
for GCC or intrin.h
for MSVC. Also, I'm aware that using C inline assembly would be a better choice, since it avoids thinking about calling conventions (see this implementation): I'd just have to think about different compiler's syntaxes. However I'd like to start practicing a bit with integrating assembly and C.
Given that I now have to write a different assembly implementation for each major assembler (I was thinking of GAS, MASM and NASM) and for each of them both for x86-64 and x86, how should I handle the fact that different machines and C compilers may use different calling conventions?
...ANSWER
Answered 2022-Mar-11 at 03:23If you really want to write, as just an exercise, an assembly function that "conforms" to all the common calling conventions for x86_64 (I know only the Windows one and the System V one), without relying on attributes or compiler flags to force the calling convention, let's take a look at what's common.
The Windows GPR passing order is rcx
, rdx
, r8
, r9
. The System V passing order is rdi
, rsi
, rdx
, rcx
, r8
, r9
. In both cases, rax
holds the return value if it fits and is a piece of POD. Technically speaking, you can get away with a "polyglot" called function if it (0) saves the union of what each ABI considers non-volatile, and (1) returns something that can fit in a single register, and (2) takes no more than 2 GPR arguments, because overlap would happen past that. To be absolutely generic, you could make it take a single pointer to some structure that would hold whatever arbitrary return data you want.
So now our arguments will come through either rcx
and rdx
or rdi
and rsi
. How do you tell which will contain the arguments? I'm actually not sure of a good way. Maybe what you could do instead is have a wrapper that puts the arguments in the right spot, and have your actual function take "padding" arguments, so that your arguments always land in rcx
and rdx
. You could technically expand to r8
and r9
this way.
QUESTION
I am trying to implement my own binary loader for learning purposes, but cannot figure out the data segment.
...ANSWER
Answered 2022-Feb-14 at 07:56QUESTION
I have trouble to grasp how to use colors in CGA/EGA/VGA video graphics modes. The video modes I'm particularly interested in are 0Dh (EGA 320x200) and 12h (VGA 640x480). Both of these modes have 4 planes, thus 16 colors.
My (probably incorrect) understanding is that I should activate a set of planes by writing a bitmask to port 03C4h
, then when I write to video memory, the data only gets written to the activated planes. Mostly I used this document to get my information, though I also encountered several other tutorials and discussions:
http://www.techhelpmanual.com/89-video_memory_layouts.html
Now I'm trying to write pixels in all possible colors in the first word in the video memory (top left part of screen). I load 1 for the initial bitmask to AH and 1 bit to BX. Then in a loop, I increment AH and shift (SHL
) the bit in BX to hit a different pixel next time. I OR
BX to A000h:0000h
to add each pixels by leaving the already existing pixels untouched.
What I'm expected to see is a line of pixels in all possible 16 EGA colors on the top left of the screen. What I actually see is 7 white and 1 bright yellow dots with black pixels in between them. What am I doing wrong?
Also, every tutorial says that I must write 0005h
to port 03CEh
before I start to use planes. What is the purpose of that? When I comment those lines out, I can still use planes (I mean, in other programs). Previously I had success using planes when I was writing to different words in video memory (so I didn't need different color pixels in one block of 16 pixels that's represented by a single word in video memory); and when I used BIOS functions (e.g. INT 10h/AH=0Ch) to write pixels, but still I want to understand how to use planar graphics without BIOS, as I believe the BIOS functions are slow.
Here is my code (indentation is optimized for 8-width tabs, so it kind of looks off here):
...ANSWER
Answered 2022-Jan-17 at 01:56Writing the word 0005h to ports 03CEh and 03CFh will select write mode 0. This is a complex mode that involves many features of the VGA but luckily for us most of these are reset when the video mode is set.
However your code still needs to do the following:
- In order to fill the VGA's internal 32-bit latch, you must perform a read-before-write operation
- Restricting output to a single or a few pixels is done using the BitMask register.
Next snippet displays a rainbow of 16 vertical lines that are 1 pixel wide:
QUESTION
I have been learning buffer overflows and i am trying to execute the following command through shellcode /bin/nc -e /bin/sh -nvlp 4455
. Here is my assembly code:
ANSWER
Answered 2021-Dec-29 at 14:12As you can see in strace
, the execve command executes as:
execve("/bin//nc", ["/bin//nc", "/bin//nc-e //bin/bash -nvlp 4455"], NULL) = 0
It seems to be taking the whole /bin//nc-e //bin/bash -nvlp 4455
as a single argument and thus thinks it's a hostname. In order to get around that, the three argv[]
needed for execve()
is pushed seperately.
argv[]=["/bin/nc", "-e/bin/bash", "-nvlp4455"]
These arguments are each pushed into edx, ecx, and ebx. since ebx needs to be /bin/nc, which was already done in the original code. we just needed to push 2nd and 3rd argv[] into ecx and edx and push it into stack. After that we just copy the whole stack into ecx, and then xor edx,edx
to set edx as NULL.
Here is the correct solution:
QUESTION
the thing is I'm training on the buffer overflow bug, and I got to the point where I just inject something into the memory, but the problem is that I have a very small space in the ESP to work with so I've made a simple "hello world" in assembly:
The Assembly code (simple hello world)
...ANSWER
Answered 2021-Dec-20 at 15:43I have learned this in the software security course. Since that was over a year ago, it is a little bit hard for me to remember all the details. I will focus on the main points.
Let's write simple assembly code first.
QUESTION
I am trying to compare the methods mentioned by Peter Cordes in his answer to the question that 'set all bits in CPU register to 1'.
Therefore, I write a benchmark to set all 13 registers to all bits 1 except e/rsp
, e/rbp
, and e/rcx
.
The code is like below. times 32 nop
is used to avoid DSB and LSD influence.
ANSWER
Answered 2021-Nov-27 at 20:04The bottleneck in all of your examples is the predecoder.
I analyzed your examples with my simulator uiCA (https://uica.uops.info/, https://github.com/andreas-abel/uiCA). It predicts the following throughputs, which closely match your measurements:
TP Link g1a 13.00 https://uica.uops.info/?code=... g1b 14.00 https://uica.uops.info/?code=... g2a 16.00 https://uica.uops.info/?code=... g2b 17.00 https://uica.uops.info/?code=... g3a 17.00 https://uica.uops.info/?code=... g3b 18.00 https://uica.uops.info/?code=... g4a 12.00 https://uica.uops.info/?code=... g4b 12.00 https://uica.uops.info/?code=...The trace table that uiCA generates provides some insights into how the code is executed. For g1a, for example, it generates the following trace:
You can see that for the 32 nops, the predecoder requires 8 cycles, and for the remaining instructions, it requires 5 cycles, which together corresponds to the 13 cycles that you measured.
You may notice that in some cycles, only a small number of instructions is predecoded; for example, in the fourth cycle, only one instruction is predecoded. This is because the predecoder works on aligned 16-byte blocks, and it can handle at most five instructions per cycle (note that some sources incorrectly claim that it can handle 6 instructions per cycle). You can find more details on the predecoder, for example how it handles instructions that cross a 16-byte boundary, in this paper.
If you compare this trace with the trace for g1b, you can see that the instructions after the nops now require 6 instead of 5 cycles to be predecoded, which is because several of the instructions in g1b are longer than the corresponding ones in g1a.
QUESTION
This code works as intended:
...ANSWER
Answered 2021-Nov-21 at 16:30Update: my patch was merged and the issue should no longer be present from NASM 2.15.06.
After some debugging and poking around in the source code I can confirm my initial suspicion that this is a bug.
The size calculation for instructions of the form Dx ?
(i.e. any Dx
which includes a uninitialized storage token ?
) where Dx
is larger than DB
internally returns the wrong size (assuming elements of 1 byte instead of the appropriate element size). This has the side effect of inconsistently altering the segment offset of any label following the instruction, causing a mismatch in the final code generation stage which is caught by a couple of checks and makes NASM error out.
Normally I would've simply reported the bug, but since NASM's GitHub repo does not have an "Issues" page active and their Bugzilla currently disallows registration I went ahead and submitted a pull request. The fix seems quite simple, unless there's something that I'm missing, in which case we'll find out (hopefully) soon.
QUESTION
my system is ubuntun 16.04 32bits nasm
I wrote a code which take an input "str_a str_b",and it will give you the length of str_a and length of str_b.
However if I input"1 1",length of str_a supposed to be 1,but when I output it ,it was 3.If I input "11 11",the output just became 5,this almost drive me crazy. And I try to print an "a" when increase length of str_a when it is"1 1",it was just printed for one time.
here is the core code
...ANSWER
Answered 2021-Oct-21 at 20:02QUESTION
In NASM, it's possible to define integer constants (equ
), however, doing the same with floating point values causes an error:
ANSWER
Answered 2021-Oct-15 at 09:44No, equ
doesn't work with non-integers. As fuz put it nicely:
The
equ
directive defines symbols. The value of a symbol is an address or an integer of the same size as an address.
Instead, you could use %define c2 3.14
to get text substitution of the macro at every point where you use it. (As opposed to equ
which evaluates an expression once, at the location of the equ
.)
That difference between equ
and macros (including %define
) matters for expressions like .len equ $ - v2
(because $
has a higher value later or in other sections), or involving something you change later with a %assign
. But it doesn't matter for numeric literal constants; they always evaluate the same way everywhere.
QUESTION
Title says it all, my pic masking works. If i send an IRQ (key-stroke) the kernel crashes. I'm using nasm. What should i do to get the exception_handler function executed when an interrupt gets send?
idt.h
...ANSWER
Answered 2021-Sep-09 at 18:50everything was right but the gdt wasn't initialized the right way
Community Discussions, Code Snippets contain sources that include Stack Exchange Network
Vulnerabilities
No vulnerabilities reported
Install nasm
Support
Reuse Trending Solutions
Find, review, and download reusable Libraries, Code Snippets, Cloud APIs from over 650 million Knowledge Items
Find more librariesStay Updated
Subscribe to our newsletter for trending solutions and developer bootcamps
Share this Page