jtag | simple commandline jtag stuff
kandi X-RAY | jtag Summary
kandi X-RAY | jtag Summary
Quick hack commandline tools to interact with Altera FPGA Virtual JTAG interfaces, using the USB Blaster device (as integrated on Terasic dev boards, etc). Not terribly fancy or optimized but only depends on libusb-1.0. Currently does not support multiple devices on the chain. jtag.c - provides simple jtag interface jtag-virtual.c - provides simple virtual jtag interface. jload.c - example of using the virtual jtag interface for a downloader interface with a CTRL/ADDR/DATA register set. CTRL[0] asserts reset, writes to DATA store to [ADDR] and auto-increment ADRR. jinfo.c - dumps idcode and virtual jtag hub and device info table. Why? Scripting the Altera quartus_stp tool in TCL was driving me nuts.
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QUESTION
I'm currently trying to set up CLion for embedded development. Running 'build' by itself creates the executable without any issues, but trying to start the debugger fails with the following error:
...ANSWER
Answered 2022-Mar-25 at 11:46"Unable to reset target" is the key line in what you have posted.
If you don't have a hardware reset line available, try changing your openOCD configuration to include:
QUESTION
I am following the "Developing Zynq UltraScale+ MPSoC Hardware Technical Training Course" on Hackster.io for a basic Hello World
program on my Ultra96 board.
Once I was at Lab2's end, I was supposed to launch my Hello World
program on the Zynq MPSoC. However, I got this warning:
ANSWER
Answered 2022-Jan-26 at 13:28I was searching around the web and found this post.
Since I am on Ubuntu, I went to the standard installation path for my Vivado/SDK. It should look a bit like this:
/tools/Xilinx/SDK/2018.3/
There, I found a "cable drivers" directory:
../data/xicom/cable_drivers/lin64/install_script/install_drivers
The content of this directory should be:
QUESTION
I am currently working on the ARM Cortex-M4 inside the NXP i.MX8M Mini. I am able to compile a project for M4 on Eclipse IDE on an Ubuntu VM. I would now like to debug on the M4 via a SEGGER Flasher ARM probe, still from Ubuntu.
My probe is well recognized by Ubuntu, and I can launch the J-Link GDB server by simply typing the command :
...ANSWER
Answered 2021-Nov-22 at 10:59As @KamilCuk said, the problem came from the udev rules.
So you just have to copy the rules provided by Segger with J-Link Software on the system:
QUESTION
I am using OpenOCD to flash code into a black-pill (STM32f103). It worked a week ago but after updating ubuntu (it's the only thing I can think of that changed) it gives me an error when flashing the code.
...ANSWER
Answered 2021-Nov-04 at 15:38Since version 0.11.0 OpenOCD doesn't create the DAP(Debug Access Point) isn't automatically created. Change the line for:
QUESTION
Has anyone managed to connect a MicroBlaze instantiated in a Xilinx FPGA to anything other than the Xilinx tools (SDK or Vitis) for download and debugging?
I'm targeting a VCU29 and have licenses from Xilinx for Vivado etc; I have already extracted the libraries, source and GCC tools and constructed a makefile that will build my applications.
I'm resigned to using Vitis to load the initial bitfile but would really like to download the code and operate the JTAG from a tool that better matches SW development flow - Eclipse with OpenOCD? Perhaps over the built-in USB->Serial->JTAG interface? I believe I'd be content with just the interface offered through GDB.
I'd really like to know if anyone has tried this with either success or failure or maybe has one of those "Why don't you just..." lateral thinking ways of solving the problem.
...ANSWER
Answered 2021-Sep-09 at 21:22Yes, my team does not use Vitis or SDK to build, deploy, or connect to MicroBlazes.
If you generate your BSP and a linker script with Vitis, you can then build using mb-gcc
and link with mb-ld
directly. To get these into your PATH, just source the settings script that Xilinx provides with their tools in /settings64.sh
.
As for loading and debugging - if you source the same script, then you will have access to xsdb
. Once you have XVC running (i.e. connecting to your board with Vivado HW manager), then you can launch xsdb
and inside run connect
or connect -xvc-url ::
if you are running on a different host. While connected, you can run targets
to identify your MicroBlaze, and then select the MicroBlaze with target 5
.
While you have the MicroBlaze selected, you can load
and run a number of debugging commands. Just run help
while connected to see your options.
QUESTION
I have the stm32 nucleo board wb55rg and am trying to flash some examples into it like blinky and a custom sample, but when am trying to flash the project into the board after building it, I am getting the same error (timed out while waiting for target halded) and I dont know how to deal with it. I was searching on internet and I found some info's about OCD and I didn't really understand. I am not using STMCubeIDE only zephyr's sample blinky. Can anyone help me with that ? I am using linux OS from VM box and a simple blinky sample from zephyr.
...ANSWER
Answered 2021-Aug-11 at 21:04I have found the problem of this issue. This board was used its previous owner has changed some togle pins on the board. So I searched for the default pins of stm32wb55rg and when I set the default pins the error was solved. Thanks a lot everyone who has made a reply to this post in order to help me find out what was going on.
QUESTION
I have been trying to get this to work for a while now. I am trying to wrap a LOT of c++ classes in swig, but I can't even get the first one to work. The error is at the bottom. Here is my interface file, setup.py, and class file.
Interface
...ANSWER
Answered 2021-Jul-16 at 20:37So I saw the answer in the link below before but didn't understand what it was saying. Basically, my process to build swig didn't include making a new _jcm.so. So pretty much the first time I ran it was it, and after that all the changes I made to the .i or the code or setup.py didn't mean anything because the _jcm.so wasn't being rewritten. In my case, I run a "make clean" from my make file and it deletes the _jcm.so. After that I build the _jcm.so again, and then run setup.py.
Simple, but hard to find.
http://swig.10945.n7.nabble.com/Req-module-object-has-no-attribute-delete-TSP-CA-td2271.html
QUESTION
I have a procedure which reads a register from a specified address: "rd_addr $jtag_master 0x00"
I'd like to remove the "$jtag_master" input, and instead use a global variable declared at the beginning of the script, which I can then use in other procedures. The initial declaration is currently implemented through use of another procedure, "set_dev".
...ANSWER
Answered 2021-Jun-07 at 00:14From the global
documentation:
This command has no effect unless executed in the context of a proc body. If the global command is executed in the context of a proc body, it creates local variables linked to the corresponding global variables
Basically, global variable_name
needs to be used inside each proc that wants to refer to the global variable of that name.
QUESTION
I'm having a hard time getting openocd to start. I attached an STM32F3 Discovery
board.
When I run openocd -f interface/stlink.cfg -f target/stm32f3x.cfg
I get the following error:
ANSWER
Answered 2021-Apr-29 at 20:47Turned out that the cable I used was just a power cable which didn't support data transmission.
With a proper mini USB cable that has all 4 lines it worked right away.
QUESTION
I am debugging board STM32f4 Discovery on Ubuntu 20.04 with openocd and arm-none-eabi-none. Things work well until yesterday. Today, when I connect the gdb to localhost:4444, following assertion happened and ocd quit:
...ANSWER
Answered 2021-Apr-26 at 01:45I found the issue: I scale up the clock speed without switching to appropriate Flash Latency so the debugger will lose the track of program address as mentioned here, in Clocks and initial settings part: https://vjordan.info/log/fpga/first-steps-with-the-stm32f4.html
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