vcd | VCD file command line viewer | Command Line Interface library

In the testbench, you declared the result signal, but it is not connected to anything. You probably intended it to be driven by the alu output of the same name. In that case, you should connect it to the instance:

Change:

Instead of using force, a more conventional approach is to add a tristate buffer to the testbench, just like you have in the design.

For SDA, create a buffer control signal (drive_sda) and a testbench data signal (sda_tb). Use a task to drive a byte and wait for the ACK.

Since SCL is not an inout, there is no need for a pullup, and it can be directly driven by clk.

I added $time to the $display statement, and this clearly showed that SDA was changing, but it was changing all at the same time (10):

You cannot do this in Chisel. Chisel only supports a small, synthesizable subset of Verilog targeting synchronous, digital design. An important part of the ethos of Chisel is that simulation matches synthesis (you're simulating what you're taping out). While I totally see the use case in clearer waveforms, delays do so much more than that and aren't really appropriate for what Chisel is trying to accomplish.

It would be nice if waveform viewers themselves provided visual cues to help make this more clear rather than forcing the user to resort to delay tricks.

As your error message states, it is illegal to make a procedural assignment to a wire. A procedural assignment is an assignment made inside an always block, for example. You declared o_led as a wire, but then you assigned to it in an always block. You should use a reg type inside an always block. Refer to IEEE Std 1800-2017, section 10.4 Procedural assignments.

Change:

Tricky one this seemed at first. I wondered if this old FFmpeg trac ticket might hold the key:

There is no stream order in mpeg-ps. what you see from ffmpeg output order is likely just if a audio or video packet comes first

But that's not actually the problem; however it is worth noting that your file has a .mpg extension, when you should be trying to output an MP4 or MKV. ".mpg" is only valid if it contains legacy MPEG-1 and MPEG-2 formats. H.264 or AAC elementary streams are invalid.

If you've not created this file yourself, it's either a mislabelled container (e.g. MKV or MP4), or someone has bizarrely muxed the streams to .mpg. Note how FFmpeg warns you of the incompatible codec during your stream reorder attempt.

MPEG-PS is a packetised format, so there's no elementary streams as such. If it's genuinely an MPEG-PS file, it may be that an audio sample appears first. Either way, you should abandon using .mpg for your formats.

See the end of this answer for how you can use FFprobe to fairly accurately identify the actual container format.

I had another think, and finally a neuron reminded me about how the -map output follows the order of assignment.

An important thing to note is that -map 0:v -map 0:a doesn't quite work how you might expect it with files containing more than one of a stream type, as that syntax matches all applicable streams of that type.

Gyan has clarified that if you have a file with exactly one video and one audio stream, -map 0:v -map 0:a will function equivalently to -map 0:1 -map 0:0.

If you want to use the 0:a syntax, if you have more than one audio for example you must address them individually, otherwise FFmpeg will group them when reordering. -map 0:a will move both audios; -map 0:a:0 will move just the first audio.

The alternative, remembering to always check stream order in every file you manipulate, is to specify absolute stream numbers in the order you wish to have them in the output. So, -map 0:1 -map 0:0 if your video is the second of two streams in the source file.

For files with one video and one audio stream, you can use either method.

I created an .MP4 file containing one H.264 video as stream 0:0 and one MP3 audio as stream 0:1.

Original file:

You need to add code in your Verilog testbench to explicitly tell iverilog to create a VCD file. The iverilog documentation states:

You can create a separate component for Chart and then just call that component in your code which is much easier.

Something like this: