CAN-X | CAN bus analyzer software
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QUESTION
This seems like it should be easy, but I can't find the answer anywhere.
Using Java 8, and Apache POI and Apache POI-OOXML 4.1.2, we are converting documents from an XML-based derivative of EPUB3 into the DOCX format. I'm new to the project, and am trying to debug something. As part of my debugging toolkit, I'd like to dump the XML in the equivalent of the document.xml file within a .docx file to a string that I can print out or save.
I tried XWPFWordExtractor
, but that seems to print out text and not XML.
I also tried .toString()
, which appears to print out the address of the object, and iterating through the results of getBodyElementsIterator()
, which isn't quite it either.
This helped me print bytes, but not the XML I wanted: Can XWPFDocument be converted to a Byte[] without saving it to a file first?
I just want something like
...ANSWER
Answered 2021-Apr-15 at 10:07A *.docx
file is simply a ZIP
archive containing multiple XML
files and other files too. So after XWPFDocument.write
the result, either a file or bytes, can be handled as such, unzipped and looked at /word/document.xml
for example.
But if one wants avoid writing out the whole document, then one needs to know that XWPFDocument
internally bases on org.openxmlformats.schemas.wordprocessingml.x2006.main.CT*
objects which all extend org.apache.xmlbeans.XmlObject
. And XmlObject.toString()
returns the XML
as String
. For the document XML
, XWPFDocument.getDocument
returns a org.openxmlformats.schemas.wordprocessingml.x2006.main.CTDocument1
which is the representaton of /word/document.xml
.
So System.out.println(docx.getDocument().toString());
will print the XML of the underlying CTDocument1
.
Unfortunately org.apache.xmlbeans.XmlObject
only represents the contents of an element or attribute, not the element or attribute itself. So when you validate or save an XmlObject
, you are validating or saving its contents, not its container. For CTDocument1
that means, it contains the body elements but not the document container itself. To get the document container itself as an XmlObject
one needs a org.openxmlformats.schemas.wordprocessingml.x2006.main.DocumentDocument
object which contains the CTDocument1
.
Example for print document XML
from XWPFDocument
:
QUESTION
This loop runs at one iteration per 3 cycles on Intel Conroe/Merom, bottlenecked on imul
throughput as expected. But on Haswell/Skylake, it runs at one iteration per 11 cycles, apparently because setnz al
has a dependency on the last imul
.
ANSWER
Answered 2019-Oct-10 at 02:04Other answers welcome to address Sandybridge and IvyBridge in more detail. I don't have access to that hardware.
I haven't found any partial-reg behaviour differences between HSW and SKL. On Haswell and Skylake, everything I've tested so far supports this model:
AL is never renamed separately from RAX (or r15b from r15). So if you never touch the high8 registers (AH/BH/CH/DH), everything behaves exactly like on a CPU with no partial-reg renaming (e.g. AMD).
Write-only access to AL merges into RAX, with a dependency on RAX. For loads into AL, this is a micro-fused ALU+load uop that executes on p0156, which is one of the strongest pieces of evidence that it's truly merging on every write, and not just doing some fancy double-bookkeeping as Agner speculated.
Agner (and Intel) say Sandybridge can require a merging uop for AL, so it probably is renamed separately from RAX. For SnB, Intel's optimization manual (section 3.5.2.4 Partial Register Stalls) says
SnB (not necessarily later uarches) inserts a merging uop in the following cases:
After a write to one of the registers AH, BH, CH or DH and before a following read of the 2-, 4- or 8-byte form of the same register. In these cases a merge micro-op is inserted. The insertion consumes a full allocation cycle in which other micro-ops cannot be allocated.
After a micro-op with a destination register of 1 or 2 bytes, which is not a source of the instruction (or the register's bigger form), and before a following read of a 2-,4- or 8-byte form of the same register. In these cases the merge micro-op is part of the flow.
I think they're saying that on SnB, add al,bl
will RMW the full RAX instead of renaming it separately, because one of the source registers is (part of) RAX. My guess is that this doesn't apply for a load like mov al, [rbx + rax]
; rax
in an addressing mode probably doesn't count as a source.
I haven't tested whether high8 merging uops still have to issue/rename on their own on HSW/SKL. That would make the front-end impact equivalent to 4 uops (since that's the issue/rename pipeline width).
- There is no way to break a dependency involving AL without writing EAX/RAX.
xor al,al
doesn't help, and neither doesmov al, 0
. movzx ebx, al
has zero latency (renamed), and needs no execution unit. (i.e. mov-elimination works on HSW and SKL). It triggers merging of AH if it's dirty, which I guess is necessary for it to work without an ALU. It's probably not a coincidence that Intel dropped low8 renaming in the same uarch that introduced mov-elimination. (Agner Fog's micro-arch guide has a mistake here, saying that zero-extended moves are not eliminated on HSW or SKL, only IvB.)movzx eax, al
is not eliminated at rename. mov-elimination on Intel never works for same,same.mov rax,rax
isn't eliminated either, even though it doesn't have to zero-extend anything. (Although there'd be no point to giving it special hardware support, because it's just a no-op, unlikemov eax,eax
). Anyway, prefer moving between two separate architectural registers when zero-extending, whether it's with a 32-bitmov
or an 8-bitmovzx
.movzx eax, bx
is not eliminated at rename on HSW or SKL. It has 1c latency and uses an ALU uop. Intel's optimization manual only mentions zero-latency for 8-bit movzx (and points out thatmovzx r32, high8
is never renamed).
- Write-only access to
ah
withmov ah, reg8
ormov ah, [mem8]
do rename AH, with no dependency on the old value. These are both instructions that wouldn't normally need an ALU uop for the 32-bit version. (Butmov ah, bl
is not eliminated; it does need a p0156 ALU uop so that might be a coincidence). - a RMW of AH (like
inc ah
) dirties it. setcc ah
depends on the oldah
, but still dirties it. I thinkmov ah, imm8
is the same, but haven't tested as many corner cases.(Unexplained: a loop involving
setcc ah
can sometimes run from the LSD, see thercr
loop at the end of this post. Maybe as long asah
is clean at the end of the loop, it can use the LSD?).If
ah
is dirty,setcc ah
merges into the renamedah
, rather than forcing a merge intorax
. e.g.%rep 4
(inc al
/test ebx,ebx
/setcc ah
/inc al
/inc ah
) generates no merging uops, and only runs in about 8.7c (latency of 8inc al
slowed down by resource conflicts from the uops forah
. Also theinc ah
/setcc ah
dep chain).I think what's going on here is that
setcc r8
is always implemented as a read-modify-write. Intel probably decided that it wasn't worth having a write-onlysetcc
uop to optimize thesetcc ah
case, since it's very rare for compiler-generated code tosetcc ah
. (But see the godbolt link in the question: clang4.0 with-m32
will do so.)reading AX, EAX, or RAX triggers a merge uop (which takes up front-end issue/rename bandwidth). Probably the RAT (Register Allocation Table) tracks the high-8-dirty state for the architectural R[ABCD]X, and even after a write to AH retires, the AH data is stored in a separate physical register from RAX. Even with 256 NOPs between writing AH and reading EAX, there is an extra merging uop. (ROB size=224 on SKL, so this guarantees that the
mov ah, 123
was retired). Detected with uops_issued/executed perf counters, which clearly show the difference.Read-modify-write of AL (e.g.
inc al
) merges for free, as part of the ALU uop. (Only tested with a few simple uops, likeadd
/inc
, notdiv r8
ormul r8
). Again, no merging uop is triggered even if AH is dirty.Write-only to EAX/RAX (like
lea eax, [rsi + rcx]
orxor eax,eax
) clears the AH-dirty state (no merging uop).- Write-only to AX (
mov ax, 1
) triggers a merge of AH first. I guess instead of special-casing this, it runs like any other RMW of AX/RAX. (TODO: testmov ax, bx
, although that shouldn't be special because it's not renamed.) xor ah,ah
has 1c latency, is not dep-breaking, and still needs an execution port.- Read and/or write of AL does not force a merge, so AH can stay dirty (and be used independently in a separate dep chain). (e.g.
add ah, cl
/add al, dl
can run at 1 per clock (bottlenecked on add latency).
Making AH dirty prevents a loop from running from the LSD (the loop-buffer), even when there are no merging uops. The LSD is when the CPU recycles uops in the queue that feeds the issue/rename stage. (Called the IDQ).
Inserting merging uops is a bit like inserting stack-sync uops for the stack-engine. Intel's optimization manual says that SnB's LSD can't run loops with mismatched push
/pop
, which makes sense, but it implies that it can run loops with balanced push
/pop
. That's not what I'm seeing on SKL: even balanced push
/pop
prevents running from the LSD (e.g. push rax
/ pop rdx
/ times 6 imul rax, rdx
. (There may be a real difference between SnB's LSD and HSW/SKL: SnB may just "lock down" the uops in the IDQ instead of repeating them multiple times, so a 5-uop loop takes 2 cycles to issue instead of 1.25.) Anyway, it appears that HSW/SKL can't use the LSD when a high-8 register is dirty, or when it contains stack-engine uops.
This behaviour may be related to a an erratum in SKL:
SKL150: Short Loops Which Use AH/BH/CH/DH Registers May Cause Unpredictable System Behaviour
Problem: Under complex micro-architectural conditions, short loops of less than 64 instruction that use AH, BH, CH, or DH registers as well as their corresponding wider registers (e.g. RAX, EAX, or AX for AH) may cause unpredictable system behaviour. This can only happen when both logical processors on the same physical processor are active.
This may also be related to Intel's optimization manual statement that SnB at least has to issue/rename an AH-merge uop in a cycle by itself. That's a weird difference for the front-end.
My Linux kernel log says microcode: sig=0x506e3, pf=0x2, revision=0x84
.
Arch Linux's intel-ucode
package just provides the update, you have to edit config files to actually have it loaded. So my Skylake testing was on an i7-6700k with microcode revision 0x84, which doesn't include the fix for SKL150. It matches the Haswell behaviour in every case I tested, IIRC. (e.g. both Haswell and my SKL can run the setne ah
/ add ah,ah
/ rcr ebx,1
/ mov eax,ebx
loop from the LSD). I have HT enabled (which is a pre-condition for SKL150 to manifest), but I was testing on a mostly-idle system so my thread had the core to itself.
With updated microcode, the LSD is completely disabled for everything all the time, not just when partial registers are active. lsd.uops
is always exactly zero, including for real programs not synthetic loops. Hardware bugs (rather than microcode bugs) often require disabling a whole feature to fix. This is why SKL-avx512 (SKX) is reported to not have a loopback buffer. Fortunately this is not a performance problem: SKL's increased uop-cache throughput over Broadwell can almost always keep up with issue/rename.
- Reading AH when it's not dirty (renamed separately) adds an extra cycle of latency for both operands. e.g.
add bl, ah
has a latency of 2c from input BL to output BL, so it can add latency to the critical path even if RAX and AH are not part of it. (I've seen this kind of extra latency for the other operand before, with vector latency on Skylake, where an int/float delay "pollutes" a register forever. TODO: write that up.)
This means unpacking bytes with movzx ecx, al
/ movzx edx, ah
has extra latency vs. movzx
/shr eax,8
/movzx
, but still better throughput.
Reading AH when it is dirty doesn't add any latency. (
add ah,ah
oradd ah,dh
/add dh,ah
have 1c latency per add). I haven't done a lot of testing to confirm this in many corner-cases.Hypothesis: a dirty high8 value is stored in the bottom of a physical register. Reading a clean high8 requires a shift to extract bits [15:8], but reading a dirty high8 can just take bits [7:0] of a physical register like a normal 8-bit register read.
Extra latency doesn't mean reduced throughput. This program can run at 1 iter per 2 clocks, even though all the add
instructions have 2c latency (from reading DH, which is not modified.)
QUESTION
I know there is this question:
How can XUnit be configured to show just the method name in the Visual Studio 2015 Test Explorer?
I tried both the solution using XML and the JSON file but the name in Text Explorer Window is still the full name with the class. I want to display the method name only as its hard to read the fully qualified names.
Its stated on this site that you can configure using XML
Configuring xUnit.net with XML
but I can't make the effect I'm expecting happen. I've restarted VS 2017 after adding an app.config file in the test project, but still nothing. Is it different for VS 2017?
...ANSWER
Answered 2017-Dec-25 at 07:56I had the same issue. I'm doing a project in VS2017 using .NET Standard and solved it by following these steps:
- In your tests project, create a file named
xunit.runner.json
- Add the following to the file:
{ "methodDisplay" : "method" }
- In the Solution Explorer, right-click on
xunit.runner.json
and select "Properties". Set Copy to Output Directory to "Copy Always".
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