Assembler | Assembler for the Digital example processor

Meson build here ; basically I have two "executable" target with a shared source, and it seems the first overlap the second for some reason although it should be sequentially.

Example :

Your first stops for further reading should probably be:

• What Every Programmer Should Know About Memory? re: cache
• https://agner.org/optimize/ re: everything else about writing efficient asm.
• https://uops.info/ for a better version of Agner Fog's instruction tables.
• See also other links in https://stackoverflow.com/tags/x86/info

so I will put out microoptimalisation until it will suffer performance problems and then I will start with profiling.

Yes, probably good to start trying stuff so you have something to profile with HW performance counters, so you can correlate what you're reading about performance stuff with what actually happens. And so you get some ideas of possible details you hadn't thought of yet before you go too far into optimizing your overall design idea. You can learn a lot about asm micro-optimization by starting with something very small scale, like a single loop somewhere without any complicated branching.

Since modern CPUs use split L1i and L1d caches and first-level TLBs, it's not a good idea to place code and data next to each other. (Especially not read-write data; self-modifying code is handled by flushing the whole pipeline on any store too near any code that's in-flight anywhere in the pipeline.)

Related: Why do Compilers put data inside .text(code) section of the PE and ELF files and how does the CPU distinguish between data and code? - they don't, only obfuscated x86 programs do that. (ARM code does sometimes mix code/data because PC-relative loads have limited range on ARM.)

Yes, making sure all your data allocations are nearby should be good for TLB locality. Hardware normally uses a pseudo-LRU allocation/eviction algorithm which generally does a good job at keeping hot data in cache, and it's generally not worth trying to manually clflushopt anything to help it. Software prefetch is also rarely useful, especially in linear traversal of arrays. It can sometimes be worth it if you know where you'll want to access quite a few instructions later, but the CPU couldn't predict that easily.

AMD's L3 cache may use adaptive replacement like Intel does, to try to keep more lines that get reused, not letting them get evicted as easily by lines that tend not to get reused. But Zen2's 512kiB L2 is relatively big by Forth standards; you probably won't have a significant amount of L2 cache misses. (And out-of-order exec can do a lot to hide L1 miss / L2 hit. And even hide some of the latency of an L3 hit.) Contemporary Intel CPUs typically use 256k L2 caches; if you're cache-blocking for generic modern x86, 128kiB is a good choice of block size to assume you can write and then loop over again while getting L2 hits.

The L1i and L1d caches (32k each), and even uop cache (up to 4096 uops, about 1 or 2 per instruction), on a modern x86 like Zen2 (https://en.wikichip.org/wiki/amd/microarchitectures/zen_2#Architecture) or Skylake, are pretty large compared to a Forth implementation; probably everything will hit in L1 cache most of the time, and certainly L2. Yes, code locality is generally good, but with more L2 cache than the whole memory of a typical 6502, you really don't have much to worry about :P

Of more concern for an interpreter is branch prediction, but fortunately Zen2 (and Intel since Haswell) have TAGE predictors that do well at learning patterns of indirect branches even with one "grand central dispatch" branch: Branch Prediction and the Performance of Interpreters - Don’t Trust Folklore

You should examine the Pageable type in Spring. Generally, what you've shown here is called something like an item resource: It's one specific Car, specified by ID at /cars/{id}. There's nothing to sort or filter. Those are applied to the collection resource /cars, perhaps something like /cars?sort=year&page=0&size=10. Spring has integrated support for automatically extracting query parameters indicating sorting and paging and passing those instructions to Spring Data repositories.

CPU hardware doesn't find registers by name, it's up to the assembler to translate names like rax to 3 or 4-bit register numbers in machine code. (And the operand-size implied by the register name is also encoded via the opcode and (lack of) prefixes).

e.g. add ecx, edx assembles to 01 d1. Opcode 01 is add r/m32, r. The 2nd byte, the ModRM 0xd1 = 0b0b11010001, encodes the operands: the high 2 bits (11) are the addressing mode, plain register, not memory (for the dest in this case, because it's 01 add r/m32, r not 03 add r32, r/m32).
The middle 3 bits are the /r field, and 010 = 2 is the register number for edx.
The low 3 bits are the r/m field, and 001 is the register number of ECX.
(The numbering goes EAX, ECX, EDX, EBX, ..., probably because 8086 was designed for asm source compatibility with 8080 - i.e. "porting" on a per-instruction basis simple enough for a machine to do automatically.)

This is what the CPU is actually decoding, and what it uses to "address" its internal registers. A simple in-order CPU without register renaming could literally use these numbers directly as addresses in an SRAM that implemented the register file. (Especially if it was a RISC like MIPS or ARM. x86 is complicated because you can use the same register numbers with different widths, and you have partial registers like AH and AL mapping onto halves of AX. But still, it's just a matter of mapping register numbers to locations in SRAM, if you didn't do register renaming.)

For x86-64, register numbers are always 4-bit, but sometimes the leading zero is implicit, e.g. in an instruction without a REX prefix like mov eax, 60. The register number is in the low 3 bits of the opcode for that special encoding.

Physically, modern CPUs use a physical register file and a register-renaming table (RAT) to implement the architectural registers. So they can keep track of the value of RAX at multiple points in time. e.g. mov eax, 60 / push rax / mov eax, 12345 / push rax can run both mov instructions in parallel, writing to separate physical registers. But still sorting out which one each push should read from.

if thats the case, i am wondering why there are only 16 registers in x86_64 architecture ...

A new ISA being designed for the high-performance use-cases where x86 competes would very likely have 32 integer registers. But shoehorning that into x86 machine code (like AVX-512 did for vector regs), wouldn't be worth the code-size cost.

x86-64 evolved out of 16-bit 8086, designed in 1979. Many of the design choices made then are not what you'd make if starting fresh now, with modern transistor budgets. (And not aiming for asm source-level compatibility with 8-bit 8080).

More architectural registers costs more bits in the machine code for each operand. More physical registers just means more out-of-order exec capability to handle more register renaming. (The physical register numbering is an internal detail.) This article measures practical out-of-order window size for hiding cache miss latency and compares it to known ROB and PRF sizes - in some cases the CPU runs out of physical registers to rename onto, before it fills the ROB, for that chosen mix of filler instructions.

, doesn't more registers means more performance ?

More architectural registers does generally help performance, but there are diminishing returns. 16 avoids a lot of store/reload work vs. 8, but increasing to 32 only saves a bit more store/reload work; 16 is often enough for compilers to keep everything they want in registers.

The fact that AMD managed to extend it to 16 registers (up from 8) is already a significant improvement. Yes, 32 integer regs would be somewhat better sometimes, but couldn't be done without redesigning the machine-code format, or with much longer prefixes (like AVX-512's 4-byte EVEX prefix, which allow 32 SIMD registers, x/y/zmm0..31 for AVX-512 instructions.)

See also:

• Modern Microprocessors A 90-Minute Guide!

• https://www.realworldtech.com/sandy-bridge/5/ - Intel Sandybridge was when Intel started using a PRF (Physical Register File) instead of keeping temporary values in the ROB (Reorder Buffer).

Related Q&As:

• How many EAX register do modern processor have?

Assembler always works one-at-a-time. To have this work in parallel, the model would need to contain 3 separate assemblers with some sort of routing logic to ensure that parts are spread across the assemblers and don't all end up in one block to be processed serially.

Okay, I've found the answer. This is special syntax to escape macro-argument name.

From the documentation:

Note that since each of the macargs can be an identifier exactly as any other one permitted by the target architecture, there may be occasional problems if the target hand-crafts special meanings to certain characters when they occur in a special position. For example:

...

problems might occur with the period character (‘.’) which is often allowed inside opcode names (and hence identifier names). So for example constructing a macro to build an opcode from a base name and a length specifier like this:

You already have the answer. Use uint64_t and __uint128_t. No intrinsics needed. This is available with modern GCC and Clang for all 64-bit targets. See Is there a 128 bit integer in gcc?

You are leaving loop1 when ah is not less than 0xff anymore.
The term less/greater is used in x86 assembly when signed numbers are compared. Number 0xff treated as signed 8bit integer has the value -1 and ah as signed byte (-128..+127), starts at 0x0f + 0x10 = 0x1f. And 31 < -1 is false on the first iteration, so loop1 is abandoned after the first call procedure1.

When comparing unsigned numbers we use term below/above. Instead of jl loop1 use jb loop1. Similary in procedure1: replace jl procedure1 with jb procedure1. (https://www.felixcloutier.com/x86/jcc)

It appeared that the memory pages were paged out. .pagein command did the trick