predictable | contenteditable text editor with predictive typeahead | Autocomplete library

Just to update this post with answer, we found the concerned EventHubs are indeed recreated, but checkpoint store was not reset. Thus, SequenceNumber presented by client (read from checkpoint store) was greater than latest sequence number at service.

As Serkant confirmed above, Sequence number is always contiguous. It can only be interrupted by recreating the eventhub. Typically, you shouldn’t have a need to delete and recreate EventHub in production. But in case you run into the situation, you should also reset checkpoint store.

HTH, Amit Bhatia

it took a bit of investigating since documentation on the issue is scarse, but i think i figured out what's happening.

profile.FirstName.ToLower().Contains(searchWord) gets translated by the driver to a $regex query.

from what i can see, the regex search in mongodb is not collation aware. so you can't use regex functionality to do diacritic insensitive searches.

however, the solution to your requirement is to create a Text Index containing all of the fields you want to search in and utilize that index to do a diacritic & case insensitive search for your search words. it will also be the most efficient way to achieve your requirement.

the one limitation of using a text index is that it won't let you search for partial matches of words such as Jo. mongodb fulltext search only works on complete words unfortunately.

here's a test program (using mongodb.entities library for brevity):

You've written:

To check if method_b has been called, you have to mock it. Also you have to mock input, as you mentioned, and make sure it returns values that will lead to the program to ended, and not to a recursion:

You could post-process the output to replace the IDs with ones that you generate yourself, or you could change the stylesheet logic to use xsl:number (or an accumulator function) instead.

In extremis, you could define your own implementation of the Saxon NodeInfo interface (perhaps subclassing an existing implementation), in which case you have full control of the generateId algorithm, but that's getting into some pretty deep water.

In fact, at least for the TinyTree model, Saxon generates the ID in two parts: a document number, and a node-number within the document. If the document doesn't change, then the second part shouldn't change. You could post-process the result to strip out the document number. But of course you have then introduced a dependency into your application, you're assuming Saxon won't change its strategy.

Based on the links provided by Egor, the current cleanest and safest way to do this seems to be as outlined here:

How to determine whether my code is running in a lua module?

which I repeat for ease of reference:

First, remove @JsonFormat(shape=JsonFormat.Shape.ARRAY) Second, add default empty constructor to classes

Re: the ultimate question: int_fast16_t is garbage for arrays because glibc on x86-64 unfortunately defines it as a 64-bit type (not 32-bit), so it wastes huge amounts of cache footprint. The question is "fast for what purpose", and glibc answered "fast for use as array indices / loop counters", apparently, even though it's slower to divide, or to multiply on some older CPUs (which were current when the choice was made). IMO this was a bad design decision.

• Cpp uint32_fast_t resolves to uint64_t but is slower for nearly all operations than a uint32_t (x86_64). Why does it resolve to uint64_t?
• How should the [u]int_fastN_t types be defined for x86_64, with or without the x32 ABI?
• Why are the fast integer types faster than the other integer types?

Generally using small integer types for arrays is good; usually cache misses are a problem so reducing your footprint is nice even if it means using a movzx or movsx load instead of a memory source operand to use it with an int or unsigned 32-bit local. If SIMD is ever possible, having more elements per fixed-width vector means you get more work done per instruction.

But unfortunately int_fast16_t isn't going to help you achieve that with some libraries, but short will, or int_least16_t.

See my comments under the question for answers to the early part: 200 stall cycles is latency, not throughput. HW prefetch and memory-level parallelism hide that. Modern Microprocessors - A 90 Minute Guide! is excellent, and has a section on memory. See also What Every Programmer Should Know About Memory? which is still highly relevant in 2021. (Except for some stuff about prefetch threads.)

Re: why L2 isn't slower than L1: out-of-order exec is sufficient to hide L2 latency, and even your LGC is too slow to stress L2 throughput. It's hard to generate random numbers fast enough to give the available memory-level parallelism much trouble.

Your Skylake-derived CPU has an out-of-order scheduler (RS) of 97 uops, and a ROB size of 224 uops (like https://realworldtech.com/haswell-cpu/3 but larger), and 12 LFBs to track cache lines it's waiting for. As long as the CPU can keep track of enough in-flight loads (latency * bandwidth), having to go to L2 is not a big deal. Ability to hide cache misses is one way to measure out-of-order window size in the first place: https://blog.stuffedcow.net/2013/05/measuring-rob-capacity

Latency for an L2 hit is 12 cycles (https://www.7-cpu.com/cpu/Skylake.html). Skylake can do 2 loads per clock from L1d cache, but not from L2. (It can't sustain 1 cache line per clock IIRC, but 1 per 2 clocks or even somewhat better is doable).

Your LCG RNG bottlenecks your loop on its latency: 5 cycles for power-of-2 array sizes, or more like 13 cycles for non-power-of-2 sizes like your "L3" test attempts¹. So that's about 1/10th the access rate that L1d can handle, and even if every access misses L1d but hits in L2, you're not even keeping more than one load in flight from L2. OoO exec + load buffers aren't even going to break a sweat. So L1d and L2 will be the same speed because they both user power-of-2 array sizes.

note 1: imul(3c) + add(1c) for x = a * x + c, then remainder = x - (x/m * m) using a multiplicative inverse, probably mul(4 cycles for high half of size_t?) + shr(1) + imul(3c) + sub(1c). Or with a power-of-2 size, modulo is just AND with a constant like (1UL<.