PGE | PGE : Parallel Game Engine | Reinforcement Learning library

I figured it out -

I used -

On "mainstream" CPUs like Skylake-X and IceLake, it's only worth using 512-bit vectors at all if you use them consistently for a lot of your program's run-time, not just for an occasional memcpy. See SIMD instructions lowering CPU frequency for the details: you don't want occasional calls to memcpy to hold your CPU frequency down to a lower max turbo.

Using AVX-512 features with 256-bit vectors (AVX-512VL) can be worth it for some things, e.g. if masking is nice, or if you use YMM16..31 to avoid VZEROUPPER.

I'd guess that glibc would only resolve memcpy to __memcpy_avx512_no_vzeroupper on systems like Knight's Landing (KNL) Xeon Phi, where the CPU is designed around AVX-512, and there's no downside to using 512-bit ZMM vectors. There's no need for vzeroupper even after using ymm0..15 on KNL. In fact vzeroupper is very slow on KNL, and definitely something to avoid, hence putting no_vzeroupper in the function name.

https://code.woboq.org/userspace/glibc/sysdeps/x86_64/multiarch/memmove-avx512-no-vzeroupper.S.html is the source for that version. It uses ZMM vectors, including ZMM0..15, so if used on a Skylake/IceLake CPU it should use vzeroupper. This version looks designed for KNL.

There would be some tiny benefit to having an AVX-512VL version that used ymm16..31 to avoid vzeroupper (to speed 32 .. 64 byte copies), without ever using ZMM registers.

And it would make sense for __memcpy_avx512_no_vzeroupper to only use ZMM16..31 so avoiding vzeroupper isn't a problem on mainstream CPUs; then it would be a usable option in code that already made heavy use of AVX-512 (and thus was already paying the CPU-frequency cost.)

There are plenty of reasons why a code can be slower with -march=native, although this is quite exceptional.

That being said, in your specific context, one possible scenario is the use of slower SIMD instructions, or more precisely different SIMD instructions finally making the program slower. Indeed, GCC vectorize loops with -O3 using the SSE instruction set on x86 processors such as yours (for backward compatibility). With -march=native, GCC will likely vectorize loops using the more advanced and more recent AVX instruction set (supported by your processor but not on many old x86 processors). While the use of AVX instruction should speed your program up, it is not always the case in few pathological cases (less efficient code generated by compiler heuristics, loops are too small to leverage AVX instructions, missing/slower AVX instructions available in SSE, alignment, transition penality, energy/frequency impact, etc.).

My guess is your program is memory bound and thus AVX instructions do not make your program faster.

You can confirm this hypothesis by enabling AVX manually using -mavx -mavx2 rather than -march=native and look if your performance issue is still there. I advise you to carefully benchmark your application using a tool like perf.

You should look in the flags section in the /proc/cpuinfo file for one of two possible values: vmx (intel) or svm (amd).

Instead of manually checking this file, you can use the grep command as in your case:

If anyone was curious, I did a simple if statement at the end:

I finally found the solution. Because I am using an old AMV processor, I needed to use an ARM based image for the emulator and not a x86 image. I was then able to run it. Unfortunately my processor was not powerful enough and was lagging as hell when launching the android emulator. Had to buy a new computer.

Using /proc/cpuinfo and free -mh along with awk, search for the strings required, using : as the field delimited, set variables accordingly, splitting the output of free -mh further into an array called arr based on " " as the delimiter. At the end, print the data in the required format using the variables created.

When searching for lines beginning with flag, we search for strings svn or vmx using awk's match function. A match will signified by the RSTART variable not being 0 and so we check this to find the type of virtualisatiion being utilised. As we have set virt to No Virtualisation at the beginning, no matches will print No Virtualisation.

tensor Flow heavily uses AVX instruction on x86 platforms. If the binary is compiled with AVX512 that is zmm registers the binary can run on supporting hardware. Hence as per the comments requested to check the instruction set via

1. objdump -M intel -S /usr/lib64/libtensorflow.so.2 | grep -i zmm and
2. print $pc in GDB to isloate the instruction.

Note: as per the update changing from Broadwell (no AVX512) to Skylake (AVX512) has solved the issue.

DPDK API rte_ipv4_frag_reassemble_packet returns NULL in 2 ocassion

1. an error occurred
2. not all fragments of the packet are collected yet

Based on the code and logs shared it looks like you are

1. sending the last fragment multiple times.
2. setting time out as cur_tsc

Note:

• the easiest way to test your packet is run it against ip_reassembly example and cross check the variance.
• if (mo == NULL) it only means not sufficient fragments are received.

[edit-1] Hence I request to model your code as dpdk example ip_reassembly since assuming rte_ipv4_frag_reassemble_packet returning NULL is not always a failure.

[edit-2] cleaning up the code and adding missing libraries I am able to get this working with right set of fragment packets