yosys | Yosys Open SYnthesis Suite

In this question, I was suggested to use the existing libraries in order to test a PLL for the iCE40 Ultra Plus 5k.

I bought the Icebreaker V1.0e board and it looks like this:

External 12 MHz oscilator is connected to the pin 35 (marked green) of the Lattice iCE40UP5k (package SG48).

Pin 35 has function: IOT_46b_G0, type: DPIO/GBIN0 and is located in bank: 0).

When I searched the library that I posted above, I found a nice primitive SB_PLL40_PAD on the page 98. This primitive's description precisely matches what was done on the Icebreaker V1.0e schematics. Here is the description:

Please observe that it matches with the pin description above! Now, I want to use this in my VHDL so for start I only wrote a VHDL wrapper for this primitive:

I am trying to formally verify my verilog FPGA design led_walker.v. So I first synthesize it to an .smt2 file:

I am using Verilog to set up FPGA so that it blinks an LED once per second. And this is one way to do it:

I have recently started using yosys, synthesized a DSP block with cmos_cells.lib and got following results:

I'm extending Yosys with a pass I made myself. In this pass, I call the techmap pass multiple times, with a path to the map to apply.

However, depending on the directory I'm in while calling my pass, the correct paths to the maps differ. Is there a variable that points to Yosys's main directory I can use?

The following code line shows how I currently call techmap.

Im currently working on the Shift-Add Algorithm (32x32 bit Multiplication) in System Verilog. System Verilog cant find any error and my code is working correctly according to GTKwave. When I synthesize my circuit with yosys, Latches will be added. And that is the Problem. I dont want Latches in my Circuit. Heres my Code:

I am trying to port some Verilog source code to SystemVerilog. This question is specific to Icarus Verilog (tested with 10.3 and 11 providing the same result), since I did not get any errors with tools (e.g. Yosys 0.9.0, Cadence Xcelium 19.09). The issue I have boils down to the following minimal example:

first of all, I'd like to say I'm not well versed in c++ or verilog at all, so I have a few problems implementing things in Yosys.

I'm currently looking for a way to implement a naive information flow tracking approach to write_verilog. The way I intent to implement it, is by creating a new var for each input/output etc. All operations types will be exchanged with simple 'or's. The doubled variables serve as taint bits. Doubling all the wires was an easy task. However when I try to add a new cell, I run into a 'std::out_of_range' error (edit: just as I was trying it again, it appears to be an 'Found error in internal cell' error now) while dumping the module. As the error happens while calling the dump_module function, I assume the module model broke.

What I've done is that for every wire in the module, I've added the same wire just with '_taint' appended to its name, its properties stays the same as the original wire, I've basically used a slightly modified version of add_wire from /passes/add.cc.

While attempting to synthesize with Yosys, I am unable to map the logic circuit using only AND, XOR, NOT, and MUX's. This is because I get an error whenever my liberty file excludes BUFX2: Error: