XMR-MinerNDK | Monroe cpu miner ndk for bit 64 & 32 on android

I found the solution.
In the example code I commented subtitle: Text(device.manufacturerName!), line.
The reason is I was using an unbranded CH340 chip, which did not have the manufacturer's name on it.

You can easily build or purchase a system with 128 vCPUs. Duplicating Google's custom hardware and firmware is another matter. 128 vCPUs is not large today.

Google Cloud publishes the processor families: CPU platforms

The Intel Ice Lake Xeon motherboards support multiple processor chips.

With a two-processor motherboard using the 40 core model (8380), 160 vCPUs are supported.

For your example, Google is using 32-core CPUs.

Note: one physical core is two vCPUs. link

I am not sure what Google is using for n2d-standard-224 which supports 224 vCPUs. That might be the Ice Lake 4 processor 28-core models.

GCloud N2 machines: 128 vCPUs in 1 chip?

Currently, the only processors that support 64 cores (128 vCPUs) that I am aware of are ARM processors from Ampere. That means Google is using one or more processor chips on a multi-cpu motherboard.

If so, Intel doesn't make them generally available for sale to the public, right?

You can buy just about any processor on Amazon, for example.

If they use several chips, how do they split the cores? Also, I assume that all cores are on the same node, do they place more than 2 CPU chips on that node or do they have chips with 56 cores (which also is a lot)?

You are thinking in terms of laptop and desktop technology. Enterprise rack mounted servers typically support two or more processor chips. This has been the norm for a long time (decades).

I believe you have typos in your Not components. The in should be in the form in=in[x], not in=[x] as you have it currently.

Conversely, your Nand components are properly formatted.

In theory it would be possible to send instruction fetch memory data directly to the IR (or to both the MB and the IR) — this would require extra hardware: wires and muxes.

You may notice that the architecture (depending on which one it is) makes use of few (one or two) busses, and this would effectively add another bus.  So, I think that all we can say is that simplicity is the reason.  Back in the day when processors were this simple, transistor counts were very limited for integrated circuits.

Going in the direction of making things more efficient, nowadays, even simple processors separate instruction (usually cache) memory from data (usually cache) memory.  This independence accomplishes a number of improvements.  MIPS, even the unpipelined single cycle processor, for example:

First, the PC (program counter) register replaces the MA for the instruction fetch side of things and the IR replaces the MB (as if loading directly into that register as you're suggesting), but let's also note that the IR can be reduced from being a true register to being wires whose output is stable for the cycle and thus can be worked on by a decode unit directly.  (Stability is gained by not sharing the instruction memory hardware with the data memory hardware; whereas with only a single memory interface, data has to be copied around and stored somewhere so the interface can be shared for both code & data.)

That saves both the cycle you're referring to: to transfer data from MB to IR, but also the cycle before to capture the data in the MB register in the first place.  (Generally speaking, enregistering some data requires a cycle, so if you can feed wires without enregistering, that's better, all other factors being the same.)

(Also depending on the architecture you're looking at, the PC on MIPS uses dedicated increment unit (adder) rather than attempting to share the main ALU and/or the busses for that increment — that could also save a cycle or two.)

Second, meanwhile the data memory can run concurrently with the instruction memory (a nice win) executing a data load from memory or store to memory in parallel with the fetch of the next instruction.  The data side also forgoes the MB register as temporary parking place, and instead can load memory data directly into a processor register (the one specified by the load instruction).

Having two dedicated memories creates an independence that reduces the need for register capture while also allowing for parallelism, of course requiring more hardware for the design.

I figured out the following with some trial and error:

• Get the "IOResources" node from the IO registry.
• Get the "KeyboardBacklight" property from that node.
• (Conditionally) convert the property value to a boolean.

I have tested this on an MacBook Air (with keyboard backlight) and on an iMac (without keyboard backlight), and it produced the correct result in both cases.

Can any x86-64 processor in 32 bit protected mode use Physical Address extension so it can address more than 4 GB of memory?

Yes.

Such an OS would be able to use more than the 64 GiB of memory (physical address space) that PAE was originally limited to; and could also still use segmentation and virtual8086 mode.

Unfortunately, 32-bit code can't use the extra registers that were added, which (depending on software) probably means up to 20% performance loss in most software (compared to 64-bit software on the same CPU).

After countless hours of searching and digging through dusty manuals, I finally found a way to determine physical keyboard layout types attached to the Mac.

By using ancient Carbon APIs, you can call KBGetLayoutType in combination with LMGetKbdType to return the desired constants. This amazingly still works in macOS Monterey.

To anyone whose looking for a solution in the future, here it is using Swift 5.5:

a. If a process has two threads, one that edits a set of variables, the other only reads said variables and never edits their values; Then do we need any sort of synchronization for guaranteeing the validity of the read values by the reading thread?

In general, yes. Otherwise, the thread editing the value could change the value only locally so that the other thread will never see the value change. This can happens because of compilers (that could use registers to read/store variables) but also because of the hardware (regarding the cache coherence mechanism used on the target platform). Generally, locks, atomic variables and memory barriers are used to perform such synchronizations.

b. Is it possible for the OS scheduling these two threads to cause the reading-thread to read a variable in a memory location in the exact same moment while the writing-thread is writing into the same memory location, or that's just a hardware/bus situation will never be allowed happen and a software designer should never care about that? What if the variable is a large struct instead of a little int or char?

In general, there is no guarantee that accesses are done atomically. Theoretically, two cores executing each one a thread can load/store the same variable at the same time (but often not in practice). It is very dependent of the target platform.

For processor having (coherent) caches (ie. all modern mainstream processors) cache lines (ie. chunks of typically 64 or 128 bytes) have a huge impact on the implicit synchronization between threads. This is a complex topic, but you can first read more about cache coherence in order to understand how the memory hierarchy works on modern platforms. The cache coherence protocol prevent two load/store being done exactly at the same time in the same cache line. If the variable cross multiple cache lines, then there is no protection.

On widespread x86/x86-64 platforms, variables having primitive types of <= 8 bytes can be modified atomically (because the bus support that as well as the DRAM and the cache) assuming the address is correctly aligned (it does not cross cache lines). However, this does not means all such accesses are atomic. You need to specify this to the compiler/interpreter/etc. so it produces/executes the correct instructions. Note that there is also an extension for 16-bytes atomics. There is also an instruction set extension for the support of transactional memory. For wider types (or possibly composite ones) you likely need a lock or an atomic state to control the atomicity of the access to the target variable.

Yes such man-in-the-middle attacks against the TPM are well-known; articles describing them seem to come out with regularity, almost on an annual basis (see here for the latest one).

The way to protect against them is session-based encryption. (see section 21 here)

To present the simplest use case, where the session is not an authorization session and is not bound to a TPM object: basically, you would start a salted session, which will ensure that only you and the TPM have access to the salt. Interception of the session start message would not help, as the salt is encrypted with a TPM key.

Then the session key is computed: