riscv-pk | V Proxy Kernel , pk , is a lightweight application

by riscv C Version: Current License: Non-SPDX

X-Ray Key Features Code Snippets(3)Community Discussions(1)Vulnerabilities Install Support

kandi X-RAY | riscv-pk Summary

riscv-pk is a C library. riscv-pk has no bugs, it has no vulnerabilities and it has low support. However riscv-pk has a Non-SPDX License. You can download it from GitHub.

RISC-V Proxy Kernel and Boot Loader.

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Support

riscv-pk has a low active ecosystem.

It has 297 star(s) with 229 fork(s). There are 62 watchers for this library.

It had no major release in the last 6 months.

There are 57 open issues and 59 have been closed. On average issues are closed in 73 days. There are 4 open pull requests and 0 closed requests.

It has a neutral sentiment in the developer community.

The latest version of riscv-pk is current.

Quality

riscv-pk has 0 bugs and 0 code smells.

Security

riscv-pk has no vulnerabilities reported, and its dependent libraries have no vulnerabilities reported.

riscv-pk code analysis shows 0 unresolved vulnerabilities.

There are 0 security hotspots that need review.

License

riscv-pk has a Non-SPDX License.

Non-SPDX licenses can be open source with a non SPDX compliant license, or non open source licenses, and you need to review them closely before use.

Reuse

riscv-pk releases are not available. You will need to build from source code and install.

Installation instructions are not available. Examples and code snippets are available.

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riscv-pk Key Features

No Key Features are available at this moment for riscv-pk.

riscv-pk Examples and Code Snippets

Initialize the robot .

python

Lines of Code : 5

License : Permissive (MIT License)

Copy

def __init__(self):
        self.velocityX=4
        self.velocityY=4
        self.X=random.randint(0,768)
        self.Y=random.randint(0,350)

Parses a tea robot .

java

Lines of Code : 4

License : Permissive (MIT License)

Copy

@GetMapping("/teapot")
    @ResponseStatus(HttpStatus.I_AM_A_TEAPOT)
    public void teaPot() {
    }

Set the number of carars in the robot .

java

Lines of Code : 3

License : Permissive (MIT License)

Copy

public void setNumberOfCarsInPark(Integer numberOfCarsInPark) {
        this.numberOfCarsInPark = numberOfCarsInPark;
    }

Community Discussions

Trending Discussions on riscv-pk

Accessing Hardware Performance Counters in RISC-V

QUESTION

Accessing Hardware Performance Counters in RISC-V

Asked 2020-Feb-08 at 18:41

I would like to instrument a program to access hardware performance counters.

I have compiled a basic Rocketchip (freechips.rocketchip.system-DefaultConfig) and am using riscv-pk to run a binary. I am running a simulation of the core in Verilator, having compiled it all with largely defaults in the UCB Chipyard project.

The C for the binary is as follows:

...

ANSWER

Answered 2020-Feb-08 at 18:41

Yes, pk runs binaries in user mode, thus it's expected that accessing a machine-level register from user space yields a illegal instruction exception:

Attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions.

(RISC-V Privileged spec 1.12-draft 2020-01-13, Section 2.1 CSR Address Mapping Conventions)

The hpmcounter* registers are accessible from user-mode (cf. Table 2.2 Currently allocated RISC-V user-level CSR addresses, RISC-V privileged spec), if and only if they are enabled in the next higher mode:

If S-mode is implemented, the same bit positions in the scounteren register analogously control access to these registers while executing in U-mode. If S-mode is permitted to access a counter register and the corresponding bit is set in scounteren, then U-mode is also permitted to access that register.

The pk snippet that enables them looks sound. The 'S' and 'U' misa bits are defined in the RISC-V privileged spec:

The “U” and “S” bits will be set if there is support for user and supervisor modes respectively.

But note that the RISC-V privileged spec also specifies (emphasis mine):

Registers mcounteren and scounteren are WARL registers that must be implemented if U-mode and S-mode are implemented. Any of the bits may contain a hardwired value of zero, indicating reads to the corresponding counter will cause an illegal instruction exception when executing in a less-privileged mode.

Perhaps your CPU doesn't implement hpmcounter3 and has it hardwired to zero?

To troubleshoot this further you can add a breakpoint inside pk, i.e. right before write_csr(scounteren, -1) and single step assembler instructions to see if the writes actually happen. If they happened you can inspect the registers to check if hpmcounter3 is hardwired to zero or not.

Source https://stackoverflow.com/questions/60048337

Community Discussions, Code Snippets contain sources that include Stack Exchange Network

Vulnerabilities

No vulnerabilities reported

Install riscv-pk

You can download it from GitHub.

Support

For any new features, suggestions and bugs create an issue on GitHub. If you have any questions check and ask questions on community page Stack Overflow .

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