software-dev | Coding Standards for the USC Biostats group | Machine Learning library

In the ST25 SDK Zip file, you will find an example of a basic Android App using the ST25 SDK Library (it is in \integration\android\examples\ST25AndroidDemoApp).

This example uses a class called “TagDiscovery” which is able to identify any ST25 Tag and to instantiate the right object. In your case, if you are only using ST25DV64K Tags, you will probably want to do something simple.

Here is what I suggest you: In your android activity, I expect that you have subscribed to receive a notification every time an NFC tag is taped (in “ST25AndroidDemoApp” example, look at enableForegroundDispatch() in onResume() function). To identify if the Intent corresponds to an “NFC Intent”, we check if the Intent’s Action is ACTION_NDEF_DISCOVERED, or ACTION_TECH_DISCOVERED or ACTION_TAG_DISCOVERED.

When this is the case, we know that it is an NFC Intent. We can then call this to get the instance of androidTag:

It seems to be broken for PIE executables
(confirmed on Arch GNU/Linux with GCC 10.2, GDB 10.1, SDE 8.33.)

Build with g++ -O2 -fno-pie -no-pie -g -march=skylake-avx512 and everything works. (I had to run gdb ./a.out instead of bare GDB; without that it couldn't find the right file even after connecting to the remote.)

The errors occur in your change_gear() function, although they are more like warnings and should not pose serious problems:

The solution is: The emulator (or the physical device) seems to needed to be rooted. Therefore only emulators images named "Google API" and not having a "Google Play Symbol" in the "Play Store Support column" are debugable.

You're trying to use '+' operator on two different data types. Your variable 'location' is not a string, it's a WindowsPath variable. You can try wrapping it with str() so that it would look like this:

Take a look at one example from your output:

Based on my understanding of the question, I recommend using the following two events on the specified processor:

• OFFCORE_RESPONSE.ALL_READS.L3_MISS.LOCAL_DRAM: This includes all cacheable data read and write transactions and all code fetch transactions, whether the transaction is initiated by a instruction (retired or not) or a prefetch or any type. Each event represents exactly a 64-byte read request to the memory controller.
• OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.LOCAL_DRAM: This includes all the code fetch accesses to the IMC.

(I think both of these event don't occur for uncacheable code fetch requests, but I've not tested this and the documentation is not clear on this.)

The "data accesses" can be measured separately from the "code accesses" by subtracting the second event from the first. These two events can be counted simultaneously on the same logical core on Haswell without multiplexing.

There are of course other transactions that do go to the IMC but are not counted by either of the two mentioned events. These include: (1) L3 writebacks, (2) uncacheable partial reads and writes from cores, (3) full WCB evictions, and (4) memory accesses from IO devices. Depending on the workload, It's not unlikely that accesses of types (1), (3), and (4) may constitute a significant fraction of total accesses to the IMC.

It seems that the sum of LLC-load-misses and LLC-store-misses will return the whole DRAM accesses (equivalently, I could use LLC-misses in Perf).

Note the following:

• The event LLC-load-misses is a perf event mapped to the native event OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_RESPONSE.
• The event LLC-store-misses is mapped to OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_RESPONSE.

These are not the events you want because:

• The ANY_RESPONSE bit indicates that the event can occur for requests that target any unit, not just the IMC.
• These events count L1 data prefetches and page walk requests, but not L2 data prefetches. You'd want to count all prefetches that consume memory bandwdith in general.

For data-only accesses, I used mem_load_uops_retired.l3_miss. It does not include stores, but seems to be OK (because stores seem to be much less frequent?!).

There are a number of issues with using mem_load_uops_retired.l3_miss on Haswell:

• There are cases where this event is unreliable, so it should be avoided if there are alternatives. Otherwise, the analysis methodology should take in to account the potential unreliability of this event count.
• The event only occurs for requests from retired loads and it omits speculative loads and all stores, which can be significant.
• Doing arithmetic with this events and other events in a meaningful way is not easy. For example, your suggestion of doing "LLC-load-misses - mem_load_uops_retired.l3_miss = DRAM Accesses for Code" is incorrect.

What are local_dram and any_response?

Not all requests that miss in the L3 go to the IMC. A typical example is memory-mapped IO requests. You said you only want the core-originated requests that go to the IMC, so local_dram is the right bit.

At first, it seems that, group (C), is a higher resolution version of the load events of group (A). But my tests show that the events in the former group is much more frequent than the latter. For example, in a simple benchmark, the number of offcore_response.all_reads.l3_miss.any_response events were twice as many as LLC-load-misses.

This is normal because offcore_response.all_reads.l3_miss.any_response is inclusive of LLC-load-misses and can easily be significantly larger.

Group (E), pertains to demand reads (i.e., all non-prefetched reads). Does this mean that, e.g.: offcore_response.all_data_rd.l3_miss.any_response - offcore_response.demand_data_rd.l3_miss.any_response = DRAM read accesses caused by prefeching?

No, because:

• the any_response bit as explained above,
• this subtraction results in only the L2 data load prefetches, not all data load hardware and software prefetches.

It seems that your code runs correctly. However, you need to call the function in order to run it. For instance, after your function, write the following:

You are treating an aggressively optimizing C compiler as if it were a macro assembler. That just plain isn't going to work. To get GCC to emit correct code in the presence of assembly inserts, you have to annotate the inserts with complete information about the registers and memory regions that are affected by the assembly code, and you have to use ancillary C statements to mesh them with the surrounding code. Even then, there are things the assembly insert cannot do at all. I urge you to scrap this entire mess and instead use the __builtin_ctzll intrinsic, as suggested in the comments on the question.

Now, to specifics. Your first function is incorrect because GCC does not support use of leave or ret inside an assembly insert. (More generally, assembly inserts may not alter the stack pointer, and may only jump to designated labels within the same function.) The correct way to use bsf from a GCC-style assembly insert is with "extended asm" with input and output operands: