JNC | JNC (Java NETCONF Client) is the name of a Java library for communicating with NETCONF agents, and a | Generator Utils library

To successfully use the BIOS.ReadSectors function 02h, you need to setup all its parameters! You didn't initialize the ES segment register, nor did you specify the head number in the DH register. Presumably you think that all registers start out with zero, but this is not the case! The only register that your bootloader receives is the DL register that holds the number for the boot drive. That will be the number that you need to provide to this function.

You are loading the additional sector at offset address 0x7E00. Because ES=0 (assuming), this is segmented address 0x0000:0x7E00. You can jmp to this address in a number of ways, but if you want to do it with a zero offset, then the segment part will have to be 0x07E0. That's how segmentation works.

You can read more about bootloaders in my answer at (https://stackoverflow.com/questions/34216893/disk-read-error-while-loading-sectors-into-memory/34382681?r=SearchResults&s=21|9.2814#34382681) and in Michael Petch's answer at (https://stackoverflow.com/questions/32701854/boot-loader-doesnt-jump-to-kernel-code/32705076?r=SearchResults&s=46|10.4269#32705076).

This is an improved version:

When an .EXE program starts in the DOS environment, the DS segment register points at the ProgramSegmentPrefix PSP. That's what we see in the included screenshot.

ASSUME DS:DATA is merily an indication for the assembler so it can verify the addressability of data items. To actually make DS point to your DATA SEGMENT, you need code like mov ax, @DATA mov ds, ax. Put it where your code begins its execution.

The number must be unsigned because you can't do properly do signed compare without also checking OF (to get the right answer in cases where the subtraction has signed overflow, e.g. on AL=127, BL=-1).

Therefore you need to use jb (unsigned below), aka jc. Talking about "negative" numbers is confusing the issue; they actually want you to do an unsigned compare. But yes the case where your code is buggy is when the numbers are different by 128 or more, like 10 < 222, so the MSB of al-bl (which goes into SF, the sign bit) is not the condition you're looking for. i.e. it's different from the carry-out (borrow) in CF.

Note that JL (signed less-than) is SF ≠ OF (https://www.felixcloutier.com/x86/jcc).

See also http://teaching.idallen.com/dat2343/10f/notes/040_overflow.txt re: signed overflow vs. carry-out.

I'm not aware of any good way to do this, I recommend AT&T syntax for GNU C inline asm (or dialect-alternatives add {%1,%0 | %0,%1} so it works both ways for GCC.) Options like -masm=intel don't get clang to substitute in bare register names the way they do for GCC.

How to generate assembly code with clang in Intel syntax? is about the syntax used for -S output, and unlike GCC it's not connected to the syntax for inline-asm input to the compiler. The behaviour of --x86-asm-syntax=intel hasn't changed: it still outputs in Intel syntax, and doesn't help you with inline asm.

You can abuse %V0 or %V[i] (instead of %0 or %[i]) to print the "naked" full-register name in the template https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html#x86Operandmodifiers, but that sucks because it only prints the full register name. Even for a 32-bit int that picked EAX, it will print RAX instead of EAX.

(It also doesn't work for "m" memory operands to get dword ptr [rsp + 16] or whatever compiler's choice of addressing mode, but it's better than nothing. Although IMO it's not better than just using AT&T syntax.)

Or you could pick hard registers like "=a"(var) and then just explicitly use EAX instead of %0. But that's worse and defeats some of the optimization benefit of the constraint system.

You do still need ".intel_syntax noprefix\n" in your template, and you should end your template with ".att_syntax" to switch the assembler back to AT&T mode to assemble the later compiler-generated asm. (Needed if you want your code to work with GCC! clang's built-in assembler doesn't merge your inline asm text into one big asm text file before assembling, it goes straight to machine code for compiler-generated instructions.)

Obviously telling the compiler it can pick any register with "=r", and then actually using your own hard-coded choices, will create undefined behaviour when the compiler picks differently. You'll step on the compilers toes and corrupt values it wanted to use later, and have it take garbage from the wrong registers as the output. IDK why you bothered to include that in your question; that would break in exactly the same way for AT&T syntax for the same fairly obvious reason.

There are two ReadByte calls here;

As you can see in the lines of Draw: dh is used for Y, dl is used for X. Both are 8-bit and the higher or lower half of the 16-bit register dx, respectively. cx seems to be used nowhere in your program. Also bp (which in other programs is often used to access variables on the stack) is available.

By the way, the push dx and pop dx is only needed to prevent dh and dl from being overwritten. On a quick glance I see mul as only command, which would do that. This could, if those are used nowhere else, not be needed for cx or bp.

Probably a better strategy for push/pop would be to save the value before it is overwritten by mul and restore it after the result of mul is not needed anymore, instead of loading and storing dx at every use on the stack.

Copying my answer from the Emscripten issue:

The reason we don't use v128.const for this is that v128.const was only recently implemented in V8. To avoid breaking origin trial users, we can't update LLVM to emit v128.const until the relevant V8 patches roll into Chrome stable. I'm keeping an eye on this dashboard to determine when will be a good time to make this change. If you're using a more recent build of Chrome or some other execution environment that does support v128.const, you can try compiling your project with the -munimplemented-simd128 flag, which will enable v128.const in LLVM (but might also introduce other changes that you don't want). Once v128.const is widely available, it will be better for LLVM to use v128.const than to load vectors from memory because that allows the engine to determine the best way to materialize vectors given the runtime platform.

It also might be worth considering porting performance-sensitive parts of your code to use the WebAssembly intrinsics header directly rather than relying on emulated SSE. That would reduce a layer of impedence mismatch between your code and the underlying machine code.

Finally, if you notice suboptimal instruction selection anywhere, it would be helpful if you could file LLVM bugs (if it's on the code -> wasm side) or V8 bugs (if it's on the wasm -> native side) about the specific issues you see. That kind of feedback is extremely valuable to us.

V8 doesn't do any auto-vectorization currently. (Source: I'm a V8 developer.) This may or may not change in the future; people are toying with ideas every now and then, but I'm not aware of any specific plans.

Wasm-SIMD is getting close to general availability (it's currently in "origin trial" experimental limited release phase), which will allow you to use SIMD instructions via WebAssembly. (Wasm being much lower level than JavaScript means that it generally gives you better control over what instruction sequence will be generated. The Wasm-SIMD instruction set in particular has been chosen such that it maps pretty well onto common hardware instructions.)

Your mov ax, word [ds:si] has an unneeded ds segment override.

This is also related to your problem with the variables, the memory accesses use ds as the default segment. So after mov ax, 0x3000 \ mov ds, ax you are not accessing your original variables any longer.

You have to reset ds to 7C0h, as your loader uses the default org 0. Your print_str function does reset ds like that. But the mov si, word [cluster] and everything between the FAT word access in .next_cluster and up to .jump uses the wrong ds. To correct this, change your code like this for example: