y86 | A Y86 pipeline CPU simulator in JavaScript

It's just a matter of perspective:

A read port: a port from which you can read: i.e. data will flow from the register file to the reading entity, thus from the perspective of the register file implementation the data connection is an output wire.

It’s an errata, and it’s listed in the errata page for the 2nd edition of the book:

Chapter 4: Processor Architecture

• p. 370, Aside tracing the pushl instruction: The second instruction byte should be 0x2f, instead of 0x28. The value of rB in the Fetch stage should be 0xf instead of 0x8.

RARS has a view which shows address, hexcode, elementary instruction and source code side by side.

You can likely get a similar hexcode/source view in the terminal using GNU standard tools (like objdump) that have RISC-V support.

Additionally there is https://github.com/michaeljclark/riscv-disassembler which may serve your needs.

Disclaimer: I am main author and maintainer of RARS.

After which stage will the pipeline know whether the conditional jump should be taken or not? Circle the correct stage

Some in-order pipelined CPUs handle branch taken/not-taken in the Decode stage, to make it only a 1 cycle bubble in the pipeline. (e.g. MIPS does this, which is why 1 branch-delay slot is enough for a classic 5-stage MIPS pipeline to fully hide the control dependency/hazard. https://en.wikipedia.org/wiki/Classic_RISC_pipeline#Control_hazards).

A design that stalls or speculates until the branch reached Execute is viable too, but lower performance.

So this question seems un-answerable, unless you have some other clue about how your y86 classic 5-stage pipeline is designed.

Resolving branch direction in Decode requires the flags to be ready sooner, so cmp or sub followed by jcc would always cause a stall for the data dependency. Checking flags is even easier than checking a register after decoding which register needs to be checked, and reading it from the register file. (MIPS doesn't have flags; it has instructions like beq $t1, $t2, target to branch on equality (which can be done with less latency than a subtract), or bltz $t1, target to check the sign bit of one reg.

It's easy enough to see that the first two quads there are bit shifted 2 to the right on disassembly, but then the next two are bit-shifted 2 to the left.

There's no 2 bit shift. There is what appears, if not paying close attention, to be a 2 nibble (8 bit) shift.

What's the pattern I'm missing here?

It's not bit shifting, it's reverse byte ordering.

Instead of repetitive patterns such as 000A000A000A try experimenting with counting patterns such as 0123456789AB

And pay attention to the most significant word, which is 0x0000 in nearly all of your examples. It appears at the end of the byte sequence, but becomes leading zeros (not even printed) in the decode.

Assuming you can use a loop and conditional branch:

The pushl %edx does not store the array to the stack, but the memory address of first element.

In your other example the first element of array2 is 32 bit integer value, which is equal to memory address of array1, so in C language terms the array2 is array of pointers.

When you fetch first element of array2 into some register, you have "pointer" (memory address) in it, and by fetching value from that address you will fetch first element of array1 (or you can modify it by some offset to fetch further elements).

This "array of pointers to arrays" pattern is often used when you have several arrays of same/similar type with different lengths and you want to store them continuously in memory, for example:

In machine code you have available (for information storage) CPU registers and memory.

Registers have fixed names and types and they are used like that, for example in x86 you can do mov eax, 0x12345678 to load 32b value into register eax.

Memory is like continuous block of byte-cells, each having it's own unique physical address (like: 0, 1, 2, ... mem_size-1). So it is like 1 dimensional byte array.

Whatever different type you want, in the end it is somehow mapped to this 1D byte array, so you have to first design how that mapping happens.

Some mappings like for example 32 bit integers have native mappings/support in the instructions, so you can for example read whole 32b int by single instruction like mov eax,[address], not having to compose it from individual bytes, but the CPU will for you read four bytes from memory at addresses: address+0, address+1, address+2 and address+3 and concatenate it into 32 bit value (on x86 CPU in little-endian order, so the byte from address+0 is in the lowest 8 bits of final value).

Other mappings like "array 2x2" don't have native support, and you have to design the memory layout and write the code accordingly to support it. For 2 dimensional arrays often mapping memory_offset = (row * columns_max + column) * single_element_byte_size is used.

Like for 16x16 matrix of 32 bit floats you can calculate memory offset (from the start of matrix data, which is at offset 0):

For each rule ruleName in your grammar, the y86Parser class will contain a class named RuleNameContext and a method named ruleName(), which will parse the input according to that rule and return an instance of the RuleNameContext class containing the parse tree. You can then use listeners or visitors to walk that parse tree.

So if you don't have a compilationUnit method or a CompilationUnitContext class, your grammar probably just doesn't have a rule named compilationUnit. Instead you should pick a rule that you do have and call the method corresponding to that rule.