vex | Run a command in the named virtualenv

You can give the h4 in CSS display: flex; and align-items: center;. Even when the icon is larger than the text it will be centered vertically.

Here's the code example:

Well, it appears I may have stumbled on to an answer. I was using the pretty much the same inputs for multiple callbacks and that could have been causing some interference with the sequencing of inputs. Once I integrated the code into one callback with multiple outputs, the problem seems to have disappeared.

what does 1A mean here? (GCC on a linux box)

It means that the length of the name is 1 followed by the letter. There are many rules on how to mangle a type, but it encodes its namespace, template parameter value and other things.

auto && should be a forwarding reference, and in this case since f() returns an A object by value, a should be deduced to rvalue reference, correct?

The typeid operator discards all top level cv and ref qualifiers.

Also, it see through references and returns the type info for the refered type instead.

From the typeid operator page:

If type is a reference type, the result refers to a std::type_info object representing the referenced type.

But yes, the type deduced is A, so you are declaring A&&. But even if a is an rvalue reference, the expression a is an lvalue.

If a is indeed rvalue reference, and since a (temporary) rvalue's lifetime could only be extended by a const lvalue ref, a should go out of scope right after this line, is that correct?

The lifetime end at the end of the scope, per the lifetime extension rules.

Now for why the typeid is different.

This is not about rvalue or forwarding references. This is the most vexing parse problem. A() is a function that returns A and has no parameters.

Use {} for initialization and you'll see the problem disappear:

Input data (for demo purpose, all strings have been cleaned):

The ResultPropertyCollection does have an internal parameterless ctor.

With reflection you can create an instance like this:

{} isn't valid there. It's used to interpolate values in JSX (like

The fact that you see throttling even for narrow SIMD instructions is a side-effect of a behavior I call implicit widening.

Basically, on modern Intel, if the upper 128-255 bits are dirty on any register in the range ymm0 to ymm15, any SIMD instruction is internally widened to 256 bits, since the upper bits need to be zeroed and this requires the full 256-bit registers in the register file to be powered and probably the 256-bit ALU path as well. So the instruction acts for the purposes of AVX frequencies as if it was 256-bit wide.

Similarly, if bits 256 to 511 are dirty on any zmm register in the range zmm0 to zmm15, operations are implicitly widened to 512 bits.

For the purposes of light vs heavy instructions, the widened instructions have the same type as they would if they were full width. That is, a 128-bit FMA which gets widened to 512 bits acts as "heavy AVX-512" even though only 128 bits of FMA is occurring.

This applies to all instructions which use the xmm/ymm registers, even scalar FP operations.

Note that this doesn't just apply to this throttling period: it means that if you have dirty uppers, a narrow SIMD instruction (or scalar FP) will cause a transition to the more conservative DVFS states just as a full-width instruction would do.

When the compiler compiles this line: