bitfields | n Booleans 1 Integer , saves columns and migrations | Data Migration library

I question the following assumption:

This didn't work. It is clear that the compiler is optimising-out much of the code related to z completely! The code then fails to function properly (running far too fast), and the size of the compiled binary drops to about 50% or so.

Looking at https://gcc.godbolt.org/z/sKdz3h8oP, it seems like the loops are actually being performed, however, for whatever reason each z++, when using a global volatile z goes from:

Sketch.cpp is compiled as as C++, including test.h. In order to support function overloading, class membership etc, C++ uses name mangling to encode these C++ features in the symbol name. As such the symbol name for some_test in Sketch.cpp is not the same as that in test.c which is compiled as C and no name mabgling is applied..

The solution is to prevent name mangling for this symbol when the header is C++ compiled by specifying that the symbol has C linkage:

The simplest way to do this would be to increment starting after 4 bits, i.e.:

Return a Seq and concatenate?

the header is in network order (big endian)

sizeof(Payload)*CHAR_BIT. This gets the size of the structure in bytes and multiplies it by the number of bits per byte (it’s technically not always 8). This works because bitfield-containing structs cannot have a size in bits which is not a multiple of CHAR_BIT. The compiler will add padding bits after the last member.

Whether to use the default register maps from the vendor or roll out your own is pretty much project-specific. If you have high requirements of portability and general source code quality, you have to make your own register map.

Some discussion on that topic can be found here: How to access a hardware register from firmware? As discussed in that post, the vendor has several reasons for rolling out their own custom, crappy register maps:

• Makes debugging register maps easier, particularly when using a crappy debugger with no specific part support (such as the various Eclipse-flavoured ones). High quality debuggers like Lauterbach, iSystem, Crossworks etc do have part support and you can watch registers just fine in them, no matter how those registers were declared in C source.
• Silicon vendors have absolutely no reason to make it easier for you to port away from their silicon to some other. Quite the contrary. Register maps are of course quite non-portable to begin with. But similarly, tool vendors don't want you to port to another compiler for the same silicon.
• Silicon vendors are notoriously incompetent when it comes to writing firmware. This has been the case for as long as everyone can remember. I wouldn't point at any particular vendor here, they are all hopelessly bad at this.

What you could do however, in case of Infineon specifically, is to ask: "Hey guys, you seem to like automotive electronics a lot. The automotive industry has been using MISRA-C since 1998. How come you still don't provide MISRA-C compliant libraries in the year 2020? You don't want automotive customers to use your products?" Lots of amusing mumbling responses to be had.

In C++ you need an extra set of braces to reflect that the initializers are in a sub-struct:

Yes, looks right.

The general pattern (for "legacy" ALU instructions that date back to 8086) for encoding op r/m, r vs. op r, r/m, and 8-bit vs. 16/32 bit does use the low 2 bits of the opcode byte in a regular pattern, but there's no need to rely on that.

Intel does fully document exactly what's going on for each encoding of each instruction in their vol.2 manual. See the Op/En column and Operand Encoding table for add for example. (See also https://ref.x86asm.net/coder64.htm which also specifies which operand is which for every opcode). These both let you know which opcodes take a ModRM byte and which don't.

These of course use Intel-syntax order. You're making your life more complicated by trying to follow manuals and tutorials while using AT&T syntax which reverses the order of the operand-list vs. Intel and AMD manuals.

e.g. 00 /r is listed as MR operand encoding, which from the table we can see is operand 1 = ModRM:r/m (r, w), so it's read and written, and encoded by the r/m field. operand 2 = ModRM:reg (r), so it's a read-only source encoded by the reg field.

Fun fact: 00 00 is add [rax], al, or AT&T add %al, (%rax)

Note that you can ask GAS to pick the either encoding: x86 XOR opcode differences