cortex-m | Low level access to Cortex-M processors

Per @jester's help, I realized I had the wrong constraint on the GCC-inline variable alias for the lock. It should have been "+m", specifying a memory address instead of a register.

I was also de-referencing the address of the lock when I should have been leaving it as a pointer.

I changed [lock] "+l"(*lock) to [lock] "+m"(lock) and it now builds.

As in the comments described, I've used indeed the wrong linker script during cross-compiling (the default linker script). It worked after specifying the linker-script (I had to use the linker-script for the specific MCU).

I fixed it by removing COPY and adding NOLOAD to the stack section. It builds and runs fine both with gcc and clang.

Files are generated from input template.

Create a file inputfile:

For what you are doing you can start simpler.

flash.s

The Problem was for the version of STM32CubeIDE 1.8

I downgraded to the STM32CubeIDE1.7 and the problem is solved.

Edited: I found the problem. According to these pictures(First for STM32CubeIDE 1.8 and Second for STM32CubeIDE 1.7)

• The STM32CubeIDE 1.8 uses the STM32CubeProgrammer 2.9 and this makes the problems but the STM32CubeIDE 1.7 uses STM32CubeProgrammer 2.8 and it makes every things work fine.

Solution2:

Alternative to downgrading stm32CubeIDE from 1.8 to 1.7 version, you can only copy and replace the below directory contents of the STM32CubeIDE 1.7:

C doesn't recognize the notion of a numeric literal whose type is smaller than int and unsigned int. On a platform where int is 32 bits, the expression (uint16_t)123 would behave as type signed int as a result of integer promotion, and it would be somewhat illogical for an expression containing a numeric literal of supposed type uint16_t to behave in a manner inconsistent with the way any other expression of that type would be processed.

TLDR: Packet drop between M4 and A7.

Hi, I ended up solving my own problem with a lot of help from PatrikF at ST Forum who suggested that DWT should work as ARM specifies it to.

Turned out the problem was very consistent packet drop between M4 and A7, exactly by factor of 2 which resulted in twice the CYCCNT. I wasted too much time looking in wrong direction but at the end of the day, I learnt the importance of packet counter.

Note that Partrik also added some recommendations on high precision counters in STM:

Maybe using STGENR is another option independant of Cortex-M4 frequency.

STGEN is running by default on HSI 64MHz which give you a resolution of about 15ns, but HSI is not an high precision oscillator (+/-1%).

alternatively, using STGEN on HSE 24MHz which is more precise (few ten of ppm) but give a resolution of about 40ns.

See also this post: https://community.st.com/s/question/0D53W00000oXAqhSAG/how-can-i-get-access-to-m4-timers-from-a7-linux-is-it-possible-

As STGEN is read using AXI bus thru async buses from Cortex-m4, it must suffer some ns of additional latency.

If you have specific code you want then...you just write it. Start with the compiled code and hand optimize as desired. The compiler cannot read your mind.

gcc 5.x.x is where gnu peaked as far as code output, it has gone down hill since. but that does not mean that version is always better than the newer versions. godbolt or just having various ones installed on your computer can help if you are trying to get the compiler to do the work for you.