chiselv | A RISC-V Core written in Chisel HDL

by carlosedp Scala Version: Current License: MIT

X-Ray Key Features Code Snippets Community Discussions Vulnerabilities Install Support

kandi X-RAY | chiselv Summary

chiselv is a Scala library. chiselv has no bugs, it has no vulnerabilities, it has a Permissive License and it has low support. You can download it from GitHub.

This project is a learning exercise for digital design, writing a RISC-V core and also have a deeper understanding of Chisel, an HDL language based on Scala. Currently the target builds a RV32I core.

Support

Quality

Security

License

Reuse

Support

chiselv has a low active ecosystem.

It has 78 star(s) with 15 fork(s). There are 6 watchers for this library.

It had no major release in the last 6 months.

There are 1 open issues and 1 have been closed. On average issues are closed in 230 days. There are 1 open pull requests and 0 closed requests.

It has a neutral sentiment in the developer community.

The latest version of chiselv is current.

Quality

chiselv has no bugs reported.

Security

chiselv has no vulnerabilities reported, and its dependent libraries have no vulnerabilities reported.

License

chiselv is licensed under the MIT License. This license is Permissive.

Permissive licenses have the least restrictions, and you can use them in most projects.

Reuse

chiselv releases are not available. You will need to build from source code and install.

Installation instructions, examples and code snippets are available.

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chiselv Key Features

No Key Features are available at this moment for chiselv.

chiselv Examples and Code Snippets

No Code Snippets are available at this moment for chiselv.

Community Discussions

No Community Discussions are available at this moment for chiselv.Refer to stack overflow page for discussions.

Community Discussions, Code Snippets contain sources that include Stack Exchange Network

Vulnerabilities

No vulnerabilities reported

Install chiselv

To install Fusesoc (requires Python3 and pip3):.

Support

Support for new boards can be added in the chiselv.core file and programming instructions in the proginfo/buildconfig.yaml together with a board template text.

Find more information at: