rocket-chip | Rocket Chip Generator

by chipsalliance Scala Version: v1.6 License: Non-SPDX

X-Ray Key Features Code Snippets Community Discussions(8)Vulnerabilities Install Support

kandi X-RAY | rocket-chip Summary

rocket-chip is a Scala library typically used in Internet of Things (IoT) applications. rocket-chip has no bugs, it has no vulnerabilities and it has medium support. However rocket-chip has a Non-SPDX License. You can download it from GitHub.

Rocket Chip Generator :rocket:

Support

Quality

Security

License

Reuse

Support

rocket-chip has a medium active ecosystem.

It has 2636 star(s) with 988 fork(s). There are 199 watchers for this library.

It had no major release in the last 12 months.

There are 196 open issues and 687 have been closed. On average issues are closed in 783 days. There are 60 open pull requests and 0 closed requests.

It has a neutral sentiment in the developer community.

The latest version of rocket-chip is v1.6

Quality

rocket-chip has 0 bugs and 0 code smells.

Security

rocket-chip has no vulnerabilities reported, and its dependent libraries have no vulnerabilities reported.

rocket-chip code analysis shows 0 unresolved vulnerabilities.

There are 0 security hotspots that need review.

License

rocket-chip has a Non-SPDX License.

Non-SPDX licenses can be open source with a non SPDX compliant license, or non open source licenses, and you need to review them closely before use.

Reuse

rocket-chip releases are available to install and integrate.

Installation instructions are not available. Examples and code snippets are available.

It has 42833 lines of code, 4209 functions and 350 files.

It has medium code complexity. Code complexity directly impacts maintainability of the code.

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rocket-chip Key Features

No Key Features are available at this moment for rocket-chip.

rocket-chip Examples and Code Snippets

No Code Snippets are available at this moment for rocket-chip.

Community Discussions

Trending Discussions on rocket-chip

Adding an MMIO peripheral to Rocket-chip as a submodule

Developing Generic AXI4 Peripheral with Chisel

Is this caused by insufficient memory?

SyncReadMem generated verilog vs. Rocketchip emitted verilog

IP block generation/testing when using diplomacy. Possible to give dummy node?

make run for RISC-V Rocket chip emulator fails

How do I make an individual Rocket tile asynchronous to the rest of the system

Taking log2Ceil of UInt

QUESTION

Adding an MMIO peripheral to Rocket-chip as a submodule

Asked 2022-Mar-03 at 16:36

I followed the MMIO Peripherals page from the Chipyard documentation to learn about adding modules to rocket-chip within Chipyard framework - and all that seems to have worked pretty well. I summed up my experiences and tried to write it in a slower pace on the pages of the Chisel Learning Journey <== adding that only if the person answering question may want to take a look and see that I've got everything working correctly. In other words, I added the MMIO with in the example package of Chipyard and it compiles, generates simulator, responds properly to toy benchmark I devised, I even see the corresponding waveforms in gtkwave.

Now, the next step I would like to take is to separate this dummy design (it literally just reads from a memory mapped register that holds a hardcoded value) from the chipyard/rocket-chip infrastructure in the sense that it is housed in a separate repo, that will become a submodule of my chipyard. So, to do that, I've started from this page and took all the steps as given there:

a new repo was created, called it my-chip
into the my-chip I added build.sbt of the following content:

...

ANSWER

Answered 2022-Mar-03 at 16:36

The error comes from the - in lazy val my-chip and package my-chip. If you want to use a - in a scala name you can wrap the name in backticks, like `my-chip`.

Source https://stackoverflow.com/questions/71237637

QUESTION

Developing Generic AXI4 Peripheral with Chisel

Asked 2022-Feb-10 at 17:09

I want to develop a generic AXI4 peripheral with Chisel. Can I use the Rocket-Chip's AMBA library for this purpose? I could only find the document in the link below on this subject;

MMIO-Peripherals

However, the example in this document is designed to be used with the Rocket-Chip. I want to develop a standalone AXI4 peripheral.

...

ANSWER

Answered 2022-Feb-09 at 16:44

Your question mentions following:

I want to develop a standalone Axi4 peripheral

When I had started developing AXI4 interfaces in Chisel, my starting point was the Chisel official documentation where they start with a typical Verilog peripheral using AXI4 for a write channel as following:

Source https://stackoverflow.com/questions/71049419

QUESTION

Is this caused by insufficient memory?

Asked 2021-Mar-19 at 22:17

This problem occurred when I used chipyard to compile Boom. Is this because of insufficient memory? I am running on a 1 core 2G cloud server.

/bin/bash: line 1: 9986 Killed java -Xmx8G -Xss8M -XX:MaxPermSize=256M -jar /home/cuiyujie/workspace/Boom/chipyard/generators/rocket-chip/sbt-launch.jar -Dsbt.sourcemode=true -Dsbt.workspace=/home/cuiyujie/workspace/Boom/chipyard/tools ";project utilities; runMain utilities.GenerateSimFiles -td /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig -sim verilator" /home/cuiyujie/workspace/Boom/chipyard/common.mk:86: recipe for target '/home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/sim_files.f' failed make: *** [/home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/sim_files.f] Error 137

When I adjusted the memory to 4G, this appeared.

Done elaborating. OpenJDK 64-Bit Server VM warning: INFO: os::commit_memory(0x00000006dc3b7000, 97148928, 0) failed; error='Cannot allocate memory' (errno=12)

There is insufficient memory for the Java Runtime Environment to continue. Native memory allocation (mmap) failed to map 97148928 bytes for committing reserved memory. An error report file with more information is saved as: /home/cuiyujie/workspace/Boom/chipyard/hs_err_pid2876.log /home/cuiyujie/workspace/Boom/chipyard/common.mk:97: recipe for target 'generator_temp' failed make: *** [generator_temp] Error 1

Should I adjust to 8G memory, or through what command to increase the memory size that the process can use?

When I adjusted the memory to 16G, this appeared.

/bin/bash: line 1: 2642 Killed java -Xmx8G -Xss8M -XX:MaxPermSize=256M -jar /home/cuiyujie/workspace/Boom/chipyard/generators/rocket-chip/sbt-launch.jar -Dsbt.sourcemode=true -Dsbt.workspace=/home/cuiyujie/workspace/Boom/chipyard/tools ";project tapeout; runMain barstools.tapeout.transforms.GenerateTopAndHarness -o /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.top.v -tho /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.harness.v -i /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.fir --syn-top ChipTop --harness-top TestHarness -faf /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.anno.json -tsaof /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.top.anno.json -tdf /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/firrtl_black_box_resource_files.top.f -tsf /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.top.fir -thaof /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.harness.anno.json -hdf /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/firrtl_black_box_resource_files.harness.f -thf /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.harness.fir --infer-rw --repl-seq-mem -c:TestHarness:-o:/home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.top.mems.conf -thconf /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig/chipyard.TestHarness.LargeBoomConfig.harness.mems.conf -td /home/cuiyujie/workspace/Boom/chipyard/sims/verilator/generated-src/chipyard.TestHarness.LargeBoomConfig -ll error" /home/cuiyujie/workspace/Boom/chipyard/common.mk:123: recipe for target 'firrtl_temp' failed make: *** [firrtl_temp] Error 137

...

ANSWER

Answered 2021-Mar-09 at 03:23

Short anwer : yes

Error 137 is thrown when your host runs out of memory.

"I am running on a 1 core 2G cloud server"

When you try to assign 8GB to the JVM, OOM-Killer says "no-no, f... no way", and kicks in sending a SIGKILL; This Killer is a proactive process that jumps in to save the system when its memory level goes too low, by killing the resource-abusive processes.

In this case, the abusive process (very abusive, indeed) is your java program, which is trying to allocate more than(*) 4 times the maximum avaliable memory in your host.

Exit Codes With Special Meanings

Source https://stackoverflow.com/questions/66539759

QUESTION

SyncReadMem generated verilog vs. Rocketchip emitted verilog

Asked 2021-Feb-24 at 17:59

I am using SyncReadMem() for sram behavioral simulation. With the generated Verilog by verilator, I hope to replace it with a commercial sram compiler compiled verilog such that I can do synthesis for the whole design including sram.

However, I noticed that the verilog emitted by SyncReadMem() is not with uniform IOs just like the sram emitted in rocketchip. I wonder how do we generate some sram verilog just like the rocketchip one, using chisel mem API like SyncReadMem()?

...

ANSWER

Answered 2021-Feb-24 at 17:59

You can use the Scala FIRRTL Compiler's "Replace Sequential Memories" pass to blackbox the memories. This is exactly what is happening with Rocket Chip.

Note that this is limited to only work if the memories have a single read port and a single write port and with read latency 1 and write latency 1.

As an example, consider the following 1r1w (one read, one write) SyncReadMem:

Source https://stackoverflow.com/questions/66344890

QUESTION

IP block generation/testing when using diplomacy. Possible to give dummy node?

Asked 2020-Sep-21 at 23:35

I've been studying rocket-chip for utilizing diplomacy and I have a decent grasp on the overall structure of how diplomacy works. (I don't understand it totally, but well enough to create some examples on my own). I would like to develop some IP in which the main objective is to have a regmap through the use of a *RegisterRouter.

If I use/modify one of the RegisterNodeExamples from rocket-chip, I get the following:

...

ANSWER

Answered 2020-Sep-21 at 23:35

Just to have an answer, I ended up using a combination of what myself and Jack Koenig went back and forth on.

If time permits I'll see if there is a way to make a "template" or LazyModule wrapper that does this for testing purposes (for each of the main protocols) and submit it to the Chisel repo.

Source https://stackoverflow.com/questions/63909300

QUESTION

make run for RISC-V Rocket chip emulator fails

Asked 2020-Apr-12 at 06:18

I'm following the README here to get set up: https://github.com/chipsalliance/rocket-chip. When I run make -j6 run in my $ROCKETCHIP/emulator directory, I get the following error message:

...

ANSWER

Answered 2020-Apr-12 at 06:18

I did not dig into this, but it seems that this is a bug recently introduced to the master branch of rocket-chip. Switching to a tagged version (v1.2.4 is the latest stable) can solve this problem.

Source https://stackoverflow.com/questions/61163412

QUESTION

How do I make an individual Rocket tile asynchronous to the rest of the system

Asked 2020-Mar-21 at 01:32

I have a multicore rocket-chip system. However I'd like one of those rocket tiles to be asynchronous from the rest.

We're trying to do that with the following:

...

ANSWER

Answered 2020-Mar-21 at 01:32

Looking at the definition of RocketCrossingKey:

Source https://stackoverflow.com/questions/60772192

QUESTION

Taking log2Ceil of UInt

Asked 2020-Feb-25 at 13:53

I'm taking log2 of following calculation:

...

ANSWER

Answered 2020-Feb-25 at 13:52

log2Ceil() is a good function to find size of a word. But be aware that it's not "synthesizable" for UInt() Wire or Reg. log2Ceil() calculation is done once at synthesize time, it's not an hardware function. Then your output signal tl_out.a.bits.size will be a constant.

If you want to find the most significant set bit, you should use the hardware functions named PriorityEncoder(Reverse(s1_row * s2_column * 4.U)).

The PriorityEncoder() return the position of least significant '1' in signal. And the Reverse() reverse the bits order in signal.

Source https://stackoverflow.com/questions/60394862

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Vulnerabilities

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Install rocket-chip

You can download it from GitHub.

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