chisel3 | Chisel 3 : A Modern Hardware Design Language

I followed the MMIO Peripherals page from the Chipyard documentation to learn about adding modules to rocket-chip within Chipyard framework - and all that seems to have worked pretty well. I summed up my experiences and tried to write it in a slower pace on the pages of the Chisel Learning Journey <== adding that only if the person answering question may want to take a look and see that I've got everything working correctly. In other words, I added the MMIO with in the example package of Chipyard and it compiles, generates simulator, responds properly to toy benchmark I devised, I even see the corresponding waveforms in gtkwave.

Now, the next step I would like to take is to separate this dummy design (it literally just reads from a memory mapped register that holds a hardcoded value) from the chipyard/rocket-chip infrastructure in the sense that it is housed in a separate repo, that will become a submodule of my chipyard. So, to do that, I've started from this page and took all the steps as given there:

1. a new repo was created, called it my-chip
2. into the my-chip I added build.sbt of the following content:

I'm using chisel based on scala with IntilliJ IDEA. The files in my project are in the same package named mypackage, and I need to import the chisel's library:

// file1.scala package mypackage import chisel3._ import chisel3.util._ /** my code */

// file2.scala package mypackage import chisel3._ import chisel3.util._ /** my code */

...

I hope to automatically/implicitly add the two libraries above to all files in mypackage, so that I don't need to repeat "import" in every file.

Thanks!

I am implementing a pulse width modulation module to learn chisel3.
The module code is:

I was trying to use queue class in chisel3.util.

I tested my source with chisel tester.

However, the results on the terminal don't match what i exepcted

My source code looks like below.

I wanted to initialize memory test code in chisel 3.

I referred the code from this website (https://www.chisel-lang.org/chisel3/docs/appendix/experimental-features#loading-memories)

I am designing a Chisel module with the following code:

The following line of code val mod_subexp_array = Vec(9, Module(new SubTaylor(fepar)).io) produces the following error:

I was looking into Chiffre as an option for fault injection in my design and noticed some when statements with printf in them.

I have created a basic module that is meant to represent a unit of memory in Chisel3: