sifive-blocks | Common RTL blocks used in SiFive 's projects | Frontend Framework library

 by   sifive Scala Version: Current License: Apache-2.0

kandi X-RAY | sifive-blocks Summary

kandi X-RAY | sifive-blocks Summary

sifive-blocks is a Scala library typically used in User Interface, Frontend Framework, React applications. sifive-blocks has no bugs, it has no vulnerabilities, it has a Permissive License and it has low support. You can download it from GitHub.

Common RTL blocks used in SiFive's projects
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              sifive-blocks has a low active ecosystem.
              It has 126 star(s) with 67 fork(s). There are 53 watchers for this library.
              OutlinedDot
              It had no major release in the last 6 months.
              There are 8 open issues and 5 have been closed. On average issues are closed in 119 days. There are 4 open pull requests and 0 closed requests.
              It has a neutral sentiment in the developer community.
              The latest version of sifive-blocks is current.

            kandi-Quality Quality

              sifive-blocks has 0 bugs and 0 code smells.

            kandi-Security Security

              sifive-blocks has no vulnerabilities reported, and its dependent libraries have no vulnerabilities reported.
              sifive-blocks code analysis shows 0 unresolved vulnerabilities.
              There are 0 security hotspots that need review.

            kandi-License License

              sifive-blocks is licensed under the Apache-2.0 License. This license is Permissive.
              Permissive licenses have the least restrictions, and you can use them in most projects.

            kandi-Reuse Reuse

              sifive-blocks releases are not available. You will need to build from source code and install.
              It has 5728 lines of code, 184 functions and 81 files.
              It has low code complexity. Code complexity directly impacts maintainability of the code.

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            sifive-blocks Key Features

            No Key Features are available at this moment for sifive-blocks.

            sifive-blocks Examples and Code Snippets

            No Code Snippets are available at this moment for sifive-blocks.

            Community Discussions

            QUESTION

            What is the purpose of the makeSink method in making IOs for a periphery
            Asked 2019-Jun-03 at 01:27

            I was following some examples of adding peripheries to the rocketchip. I used the sifive-blocks as reference.

            below is an example from their I2C example (I hope it's ok to post it here)

            ...

            ANSWER

            Answered 2019-Jun-03 at 01:27

            I'm not an expert in rocket-chip's Diplomacy, but from glancing at the code, I think makeIO and makeSink do fundamentally different things.

            makeIO takes the BundleBridgeSource and materializes ports in the Chisel Module implementation for driving that source. There is the same method on BundleBrigeSink. I believe this method is the way you take either side of a Bundle bridge and interface with it in the actual Chisel part of the generator (as opposed to the Diplomatic part).

            makeSink turns a BundleBridgeSource into a BundleBridgeSink. It doesn't materialize Chisel ports and it stays in Diplomacy world rather than in the Chisel world.

            In the example from I2C you included, note how the part with makeSink is a trait to mix into something that extends BaseSubsystem, it's diplomatic. On the other hand, HasPeripheryI2CModuleImp which has the makeIO extends LazyModuleImp which is the Chisel part. One way to think about this is two different "views" of the same thing. Chisel and Diplomacy use different objects, thus i2cNodes (diplomatic) vs. i2c (Chisel).

            Source https://stackoverflow.com/questions/56420115

            QUESTION

            How to add a sbus master to rocket-chip periphery
            Asked 2018-Sep-07 at 00:28

            I'm trying to implement a DMA like periphery to the rocket chip. Meaning a module that is hooked to the pbus, and controlled by registers. it also has a master hooked to the sbus.

            I followed the sifive format to attach registers controlled peripheries without any problems. My question is how do I add the sbus master ?, the bellow is what I've tried before getting to dead end.

            To the attach parameters class I've added the sbus:

            ...

            ANSWER

            Answered 2018-Sep-04 at 19:03

            I don't understand what is going wrong in your "Update", but this should work:

            Source https://stackoverflow.com/questions/52142504

            Community Discussions, Code Snippets contain sources that include Stack Exchange Network

            Vulnerabilities

            No vulnerabilities reported

            Install sifive-blocks

            You can download it from GitHub.

            Support

            For any new features, suggestions and bugs create an issue on GitHub. If you have any questions check and ask questions on community page Stack Overflow .
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          • HTTPS

            https://github.com/sifive/sifive-blocks.git

          • CLI

            gh repo clone sifive/sifive-blocks

          • sshUrl

            git@github.com:sifive/sifive-blocks.git

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