sifive-blocks | Common RTL blocks used in SiFive 's projects | Frontend Framework library
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kandi X-RAY | sifive-blocks Summary
Common RTL blocks used in SiFive's projects
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QUESTION
I was following some examples of adding peripheries to the rocketchip. I used the sifive-blocks as reference.
below is an example from their I2C example (I hope it's ok to post it here)
...ANSWER
Answered 2019-Jun-03 at 01:27I'm not an expert in rocket-chip's Diplomacy, but from glancing at the code, I think makeIO
and makeSink
do fundamentally different things.
makeIO
takes the BundleBridgeSource
and materializes ports in the Chisel Module implementation for driving that source. There is the same method on BundleBrigeSink
. I believe this method is the way you take either side of a Bundle bridge and interface with it in the actual Chisel part of the generator (as opposed to the Diplomatic part).
makeSink
turns a BundleBridgeSource
into a BundleBridgeSink
. It doesn't materialize Chisel ports and it stays in Diplomacy world rather than in the Chisel world.
In the example from I2C
you included, note how the part with makeSink
is a trait to mix into something that extends BaseSubsystem
, it's diplomatic. On the other hand, HasPeripheryI2CModuleImp
which has the makeIO
extends LazyModuleImp
which is the Chisel part. One way to think about this is two different "views" of the same thing. Chisel and Diplomacy use different objects, thus i2cNodes
(diplomatic) vs. i2c
(Chisel).
QUESTION
I'm trying to implement a DMA like periphery to the rocket chip. Meaning a module that is hooked to the pbus, and controlled by registers. it also has a master hooked to the sbus.
I followed the sifive format to attach registers controlled peripheries without any problems. My question is how do I add the sbus master ?, the bellow is what I've tried before getting to dead end.
To the attach parameters class I've added the sbus:
...ANSWER
Answered 2018-Sep-04 at 19:03I don't understand what is going wrong in your "Update", but this should work:
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