flag | class interface for working with feature flags | Frontend Framework library
kandi X-RAY | flag Summary
kandi X-RAY | flag Summary
Feature flagging for React and Redux with strong TypeScript support
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Currently covering the most popular Java, JavaScript and Python libraries. See a Sample of flag
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def get_flag_value(self, wanted_flag_name):
"""Returns the value of a TensorTracer flags.
Args:
wanted_flag_name: the name of the flag we are looking for.
Returns:
A pair where the first element indicates if the flag is
def set_log_device_placement(enabled):
"""Turns logging for device placement decisions on or off.
Operations execute on a particular device, producing and consuming tensors on
that device. This may change the performance of the operation or re
def match_next_flag(flags, pos):
"""Returns the match for the next TensorTracer flag.
Args:
flags: a string that contains the flags.
pos: where in flags to start the search.
Returns:
A pair where the first element i
#!/usr/bin/env bash
case $BASH_VERSION in '') echo "ERROR: must be run with bash" >&2; exit 1;; esac
faults_found=0
encryption_required_re='^[[:space:]]*(username|password|key)=(.*)$'
encryption_present_re='ENC[(][^)]+[)]'
for fil
class ImageCardWithButton: UIView {
lazy var cardImage: UIImageView = {
let image = UIImageView()
image.translatesAutoresizingMaskIntoConstraints = false // To flag that we are using Constraints to set the layout
row_number() over (order by [Timestamp])
- row_number() over (partition by ProductionState
order by [Timestamp])
row_number() over (order by [Timestamp])
+ row_number() over (parti
ffmpeg \
# Some basic options
-hide_banner \
-loglevel verbose \
# Scaling flags for the input
# The print_info flag is very useful to debug cases when swscale is applied automatically!
# The other flags ensure ffmpeg favors
-- rank via ascending row_number + descending row_number
SELECT
MIN(ValidFrom) AS ValidFrom
, MAX(ValidTo) AS ValidTo
, Num
, [ID Number]
-- , Rnk
FROM
(
SELECT *
, Rnk = ROW_NUMBER() OVER (PARTITION BY [ID Number] ORDER BY Valid
$(".js-country-list").select2({
templateResult: formatState,
templateSelection: formatState
});
// Template function which adds CSS flag and displays country name
function flagTemplate(country){
return $("
var canvas, ctx, flag, coords, cntnr, dot_flag;
function _InitDraw() {
flag = false;
coords = {
pX: 0,
cX: 0,
pY: 0,
cY: 0
};
cntnr = {
minX: document.body.offsetWidt
Community Discussions
Trending Discussions on flag
QUESTION
Here is a basic Spinlock implemented with std::atomic_flag
.
The author of the book claims that second while in the lock()
boosts performance.
ANSWER
Answered 2022-Jan-28 at 05:13Reading a memory address does not clear the cache line.
Writing does.
So in a modern computer, there is RAM, and there are multiple layers of cache "around" the CPU (they are called L1, L2 and L3 cache, but the important part is that they are layers, and the CPU is at the middle). In a multi-core system, often the outer layers are shared; the innermost layer is usually not, and is specific to a given CPU.
Clearing the cache line means informing every other cache holding this memory "the data you own may be stale, throw it out".
Test and set writes true and atomically returns the old value. It clears the cache line, because it writes.
Test does not write. If you have another thread unsynchronized with this one, it reading the cache of this memory doesn't have to be poked.
The outer loop writes true, and exits if it replaced false. The inner loop waits until there is a false visible, then falls to outer loop. The inner loop need not clear every other cpu's cache status of the value of the atomic flag, but the outer has to (as it could change the false to true). As spinning could go on for a while, avoiding continuous cache clearing seems like a good idea.
QUESTION
I made a bubble sort implementation in C, and was testing its performance when I noticed that the -O3
flag made it run even slower than no flags at all! Meanwhile -O2
was making it run a lot faster as expected.
Without optimisations:
...ANSWER
Answered 2021-Oct-27 at 19:53It looks like GCC's naïveté about store-forwarding stalls is hurting its auto-vectorization strategy here. See also Store forwarding by example for some practical benchmarks on Intel with hardware performance counters, and What are the costs of failed store-to-load forwarding on x86? Also Agner Fog's x86 optimization guides.
(gcc -O3
enables -ftree-vectorize
and a few other options not included by -O2
, e.g. if
-conversion to branchless cmov
, which is another way -O3
can hurt with data patterns GCC didn't expect. By comparison, Clang enables auto-vectorization even at -O2
, although some of its optimizations are still only on at -O3
.)
It's doing 64-bit loads (and branching to store or not) on pairs of ints. This means, if we swapped the last iteration, this load comes half from that store, half from fresh memory, so we get a store-forwarding stall after every swap. But bubble sort often has long chains of swapping every iteration as an element bubbles far, so this is really bad.
(Bubble sort is bad in general, especially if implemented naively without keeping the previous iteration's second element around in a register. It can be interesting to analyze the asm details of exactly why it sucks, so it is fair enough for wanting to try.)
Anyway, this is pretty clearly an anti-optimization you should report on GCC Bugzilla with the "missed-optimization" keyword. Scalar loads are cheap, and store-forwarding stalls are costly. (Can modern x86 implementations store-forward from more than one prior store? no, nor can microarchitectures other than in-order Atom efficiently load when it partially overlaps with one previous store, and partially from data that has to come from the L1d cache.)
Even better would be to keep buf[x+1]
in a register and use it as buf[x]
in the next iteration, avoiding a store and load. (Like good hand-written asm bubble sort examples, a few of which exist on Stack Overflow.)
If it wasn't for the store-forwarding stalls (which AFAIK GCC doesn't know about in its cost model), this strategy might be about break-even. SSE 4.1 for a branchless pmind
/ pmaxd
comparator might be interesting, but that would mean always storing and the C source doesn't do that.
If this strategy of double-width load had any merit, it would be better implemented with pure integer on a 64-bit machine like x86-64, where you can operate on just the low 32 bits with garbage (or valuable data) in the upper half. E.g.,
QUESTION
I'm looking for a way to have all keys / values pair of a nested object.
(For the autocomplete of MongoDB dot notation key / value type)
...ANSWER
Answered 2021-Dec-02 at 09:30In order to achieve this goal we need to create permutation of all allowed paths. For example:
QUESTION
Today (7.8.2021) Discord.js v13 has been released. So I upgraded my previous Discord.js installation with
npm i discord.js@latest
and then adapted my basic index.js file to this state (I followed the Discord.js Guide):
...ANSWER
Answered 2021-Sep-19 at 04:04One of the prerequisites for using Discord.js v13 is that you need to use NodeJS v16.6 or higher (emphasis mine):
The Fix:v13 requires Node 16.6 or higher to use, so make sure you're up to date. To check your Node version, use node -v
The fix is to update your node version, you can confirm your current node version by running node -v
. There are a variety of different ways to update node, one way is to run the following commands if you're using Linux / iOS:
QUESTION
I've got a very simple FormRequest
class in a Laravel project. Two methods, both of which return a simple array that's partially populated by a method, but the IDE treats them differently.
ANSWER
Answered 2021-Oct-06 at 17:41If a function only depends on other pure functions, then it is also pure. Since getPhoneNumberRules()
just returns a fixed array, it's pure, so rules()
is also pure.
But messages()
calls getPhoneNumberMessage()
, which calls the __()
function that can return a different localized message if the location state changes, so it's not pure.
QUESTION
I am curious about the vastly different performance characteristics of running x86-64 binaries on the Apple M1 platform using Rosetta 2 vs. emulation, for example what Docker Desktop currently does using QEMU.
I understand why emulation is so slow, but an explanation for why Rosetta 2 is so fast has been detailed in this Twitter thread: https://twitter.com/ErrataRob/status/1331735383193903104
The gist of that explanation is that under usual circumstances, arm and x86 have opposite (and incompatible) memory addressing schemes which require significant emulation overhead, but the M1 chip addresses this with a hardware optimization that allows it to access memory using both addressing schemes. Effectively, when Rosetta 2-emulated instructions are being run, a flag is set to let the processor know to use the x86-style addressing scheme.
Assuming this explanation is reasonable (and if anyone has better-sourced reporting than the above Twitter thread I would appreciate it in the comments for inclusion), is it technically plausible that this optimization could be leveraged for full hardware emulation, for example running x86-64 Linux Docker containers, or running a full x86-64 Windows desktop virtual machine a la VMware Fusion/VirtualBox? Or, does the separate operating system layer in those scenarios preclude being able to leverage the memory ordering optimization?
Separately, is this processor mode (flags or instructions) documented and published for 3rd-party use, or is it private to Apple only?
...ANSWER
Answered 2021-Sep-04 at 20:09Not memory addressing, memory ordering. i.e. for lock-free atomics used for inter-thread synchronization - in x86, every asm load/store is acquire/release respectively. (With real x86 CPUs doing speculative early loads so performance doesn't suffer under normal conditions when a single thread is operating on memory that other threads aren't writing.)
M1 has hardware support for a mode like that, as well as a weakly-ordered mode to run native AArch64 code most efficiently. See
- https://singhkays.com/blog/apple-silicon-m1-black-magic/#performance-must-suck-when-trying-to-emulate-x86-on-arm-right
- https://www.reddit.com/r/hardware/comments/i0mido/apple_silicon_has_a_runtime_toggle_for_tso_to/.
And yes, https://github.com/saagarjha/TSOEnabler is open-source software to toggle that support. But it's a kernel extension, and code signing makes it tricky to get MacOS to allow it, and you have to sign it or disable signature verification or something:
Supposedly, you should be able to use this if you build and sign the kernel extension (disabling SIP if you aren't using a KEXT signing certificate) and drag it into /Library/Extensions. A dialog should come up to prompt you to enable the extension in the Security & Privacy preferences pane, you allow it from there and restart, and it will be installed. (If you're not seeing it, the permissions on the extension might be wrong: try a chown -R root:wheel.) In practice this can go wrong in many ways, and I have had luck by "resetting everything" and trying to install after doing the following:
[...] see the link for the list of steps
So yes, it's plausible that QEMU's x86 emulation could use the same hardware support that Rosetta-2's x86 emulation does. They're both x86 emulators.
And as you say, the main issue is Apple providing public APIs for enabling the HW mode so people don't have to install this kernel module manually; I'm sure most people wouldn't want to do that. I don't know much about the software situation, I was more interested in the CPU-architecture details.
QUESTION
My react native project worked fine yesterday. But this morning, after I tried to run it again, it gave me the following error:
...ANSWER
Answered 2021-Aug-28 at 09:59Apparently, it may be a problem with the babel. Copy the folder @babel
(specifically @babel/core
) that is in the node_modules of a working project into the new project and it runs without problems.
It may be due to an update they did a couple of hours ago.
You can also remove the current @babel/core
from the package.json and install this version npm install --save-dev @babel/core@latest
.
Or use this:
@babel file
: https://drive.google.com/file/d/1-z_4H_z4x075unZqZD41WYUwY_hsrKox/view.
Or replace the following codes in your package.json
file then npm install
.
QUESTION
We have been running a service using NestJS and TypeORM on fully managed CloudRun without issues for several months. Yesterday PM we started getting Improper path /cloudsql/{SQL_CONNECTION_NAME} to connect to Postgres Cloud SQL instance "{SQL_CONNECTION_NAME}"
errors in our logs.
We didn't make any server/SQL changes around this timestamp. Currently there is no impact to the service so we are not sure if this is a serious issue.
This error is not from our code, and our third party modules shouldn't know if we use Cloud SQL, so I have no idea where this errors come from.
My assumption is Cloud SQL Proxy or any SQL client used in Cloud Run is making this error. We use --add-cloudsql-instances flag when deploying with "gcloud run deploy" CLI command.
Link to the issue here
...ANSWER
Answered 2021-Jun-11 at 17:27This log was recently added in the Cloud Run data path to provide more context for debugging CloudSQL connectivity issues. However, the original logic was overly aggressive, emitting this message even for properly working CloudSQL connections. Your application is working correctly and should not receive this warning.
Thank you for reporting this issue. The fix is ready and should roll out soon. You should not see this message anymore after the fix is out.
QUESTION
I have a huge memory block (bit-vector) with size N bits within one memory page, consider N on average is 5000, i.e. 5k bits to store some flags information.
At a certain points in time (super-frequent - critical) I need to find the first bit set in this whole big bit-vector. Now I do it per-64-word, i.e. with help of __builtin_ctzll
). But when N grows and search algorithm cannot be improved, there can be some possibility to scale this search through the expansion of memory access width. This is the main problem in a few words
There is a single assembly instruction called BSF
that gives the position of the highest set bit (GCC's __builtin_ctzll()
).
So in x86-64 arch I can find the highest bit set cheaply in 64-bit words.
But what about scaling through memory width?
E.g. is there a way to do it efficiently with 128 / 256 / 512 -bit registers?
Basically I'm interested in some C API function to achieve this, but also want to know what this method is based on.
UPD: As for CPU, I'm interested for this optimization to support the following CPU lineups:
Intel Xeon E3-12XX, Intel Xeon E5-22XX/26XX/E56XX, Intel Core i3-5XX/4XXX/8XXX, Intel Core i5-7XX, Intel Celeron G18XX/G49XX (optional for Intel Atom N2600, Intel Celeron N2807, Cortex-A53/72)
P.S. In mentioned algorithm before the final bit scan I need to sum k (in average 20-40) N-bit vectors with CPU AND (the AND result is just a preparatory stage for the bit-scan). This is also desirable to do with memory width scaling (i.e. more efficiently than per 64bit-word AND)
Read also: Find first set
...ANSWER
Answered 2021-May-25 at 21:12You may try this function, your compiler should optimize this code for your CPU. It's not super perfect, but it should be relatively quick and mostly portable.
PS length
should be divisible by 8 for max speed
QUESTION
I'm looking for a workaround, which will probably involve patching libstdc++ headers. Preserving binary compatibility is preferred but not obligatory, since I'm not using any precompiled C++ code except libstdc++.
I want to keep the std::call_once
interface, since I'm trying to compile third-party code that uses is, which I don't want to change.
Here's my code:
...ANSWER
Answered 2021-Apr-28 at 19:42One way you might work around this is to take advantage of the fact that static
variables are, since C++11, initialised in a threadsafe way. Example:
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