rsp | A Really Simple Proxy | Proxy library

If you read the assembler code from the top you will see that it reaches .L3, plus it also jumps to it with jne .L3, which is your for loop in C.

Whenever you fix issues, start by the first one (cause solving that may remove the remaining), which in you case seems to be:

llvm-objdump -S should work in the same way that it does for native object files.

If you are looking for nice display of code that lacks debug info you might also want to take a look at wasm-decompile which is part of the wabt project. Its able to do a much better job of making something readable than normal/native decompilers.

I'm compiling with GL_GLEXT_PROTOTYPES=1.

Well, don't do that. That is never going to work in a portable way. On windows, the opengl32.dll always exports only the functions which are in OpenGL 1.1, and for everything beyond that, you have to rely to the OpenGL extension loading mechanism at runtime.

I have tried:

• [...]
• Adding GLEW

That's a step in the right direction. But this does not make things to magically work. A GL loader like GLEW typically brings its own header as a replacement for GL.h and glext.h etc., and the typical GL loader (like GLEW) simply re-define every GL functions as a macro, like this:

The slow version:

Note that the sub rax, 1 \ jne pair goes right across the boundary of the ..80 (which is a 32byte boundary). This is one of the cases mentioned in Intels document regarding this issue namely as this diagram:

So this op/branch pair is affected by the fix for the JCC erratum (which would cause it to not be cached in the µop cache). I'm not sure if that is the reason, there are other things at play too, but it's a thing.

In the fast version, the branch is not "touching" a 32byte boundary, so it is not affected.

There may be other effects that apply. Still due to crossing a 32byte boundary, in the slow case the loop is spread across 2 chunks in the µop cache, even without the fix for JCC erratum that may cause it to run at 2 cycles per iteration if the loop cannot execute from the Loop Stream Detector (which is disabled on some processors by an other fix for an other erratum, SKL150). See eg this answer about loop performance.

To address the various comments saying they cannot reproduce this, yes there are various ways that could happen:

• Whichever effect was responsible for the slowdown, it is likely caused by the exact placement of the op/branch pair across a 32byte boundary, which happened by pure accident. Compiling from source is unlikely to reproduce the same circumstances, unless you use the same compiler with the same setup as was used by the original poster.
• Even using the same binary, regardless of which of the effects is responsible, the weird effect would only happen on particular processors.

This is a bug in version 6.0.0 of the Google Mobile Ads Unity plugin. Tracked in https://github.com/googleads/googleads-mobile-unity/issues/1613.

The issue was in fact due to the FscToolPath evaluating to an empty string.

Existing error message accurately conveys the issue; it’s not F#-specific. Something in the .props/.targets files evaluates to dotnet $(PathToFsc) some/file.rsp and the variable $(PathToFsc) (or whatever is in your build scripts) is evaluating to an empty string. The final command that’s executed is then dotnet some/file.rsp and the normal dotnet behavior is to look for dotnet- as an executable.

The second factor was that the location of FSC did change due to an update of Visual Studio on the VM Image.

Not an answer, but I wonder if it's related to this: stackoverflow.com/questions/67800998/… - it seems things may have moved between VS 16.9 and 16.10.

Finally why it impacted me was because I was setting the FscCompilerPath manually due to a TypeProvider that did not support the dotnet core pipeline due to a dependency on System.Data.SqlClient.

The language doesn't define where arguments to functions are stored. Different ABIs, for different platforms, define this.

Typically, a function argument, before any optimization, is stored on the stack. A reference is no different in this respect. What's actually stored would be a pointer to the refered-to object. Think of it this way:

Your first stops for further reading should probably be:

• What Every Programmer Should Know About Memory? re: cache
• https://agner.org/optimize/ re: everything else about writing efficient asm.
• https://uops.info/ for a better version of Agner Fog's instruction tables.
• See also other links in https://stackoverflow.com/tags/x86/info

so I will put out microoptimalisation until it will suffer performance problems and then I will start with profiling.

Yes, probably good to start trying stuff so you have something to profile with HW performance counters, so you can correlate what you're reading about performance stuff with what actually happens. And so you get some ideas of possible details you hadn't thought of yet before you go too far into optimizing your overall design idea. You can learn a lot about asm micro-optimization by starting with something very small scale, like a single loop somewhere without any complicated branching.

Since modern CPUs use split L1i and L1d caches and first-level TLBs, it's not a good idea to place code and data next to each other. (Especially not read-write data; self-modifying code is handled by flushing the whole pipeline on any store too near any code that's in-flight anywhere in the pipeline.)

Related: Why do Compilers put data inside .text(code) section of the PE and ELF files and how does the CPU distinguish between data and code? - they don't, only obfuscated x86 programs do that. (ARM code does sometimes mix code/data because PC-relative loads have limited range on ARM.)

Yes, making sure all your data allocations are nearby should be good for TLB locality. Hardware normally uses a pseudo-LRU allocation/eviction algorithm which generally does a good job at keeping hot data in cache, and it's generally not worth trying to manually clflushopt anything to help it. Software prefetch is also rarely useful, especially in linear traversal of arrays. It can sometimes be worth it if you know where you'll want to access quite a few instructions later, but the CPU couldn't predict that easily.

AMD's L3 cache may use adaptive replacement like Intel does, to try to keep more lines that get reused, not letting them get evicted as easily by lines that tend not to get reused. But Zen2's 512kiB L2 is relatively big by Forth standards; you probably won't have a significant amount of L2 cache misses. (And out-of-order exec can do a lot to hide L1 miss / L2 hit. And even hide some of the latency of an L3 hit.) Contemporary Intel CPUs typically use 256k L2 caches; if you're cache-blocking for generic modern x86, 128kiB is a good choice of block size to assume you can write and then loop over again while getting L2 hits.

The L1i and L1d caches (32k each), and even uop cache (up to 4096 uops, about 1 or 2 per instruction), on a modern x86 like Zen2 (https://en.wikichip.org/wiki/amd/microarchitectures/zen_2#Architecture) or Skylake, are pretty large compared to a Forth implementation; probably everything will hit in L1 cache most of the time, and certainly L2. Yes, code locality is generally good, but with more L2 cache than the whole memory of a typical 6502, you really don't have much to worry about :P

Of more concern for an interpreter is branch prediction, but fortunately Zen2 (and Intel since Haswell) have TAGE predictors that do well at learning patterns of indirect branches even with one "grand central dispatch" branch: Branch Prediction and the Performance of Interpreters - Don’t Trust Folklore