vmread | A library to read/write memory to Windows on KVM | Monitoring library
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A library to read/write memory to Windows on KVM
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QUESTION
I'm having an issue implementing EPT in a hypervisor I'm developing. I'm receiving error no. 48 (EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures) with an EXIT_QUALIFICATION of 0x81 upon doing a VMLAUNCH. I've checked the page allocation logic and made sure GUEST_CR3 = HOST_CR3. I'm not sure why is this happening. I'm running on VMWare on a Linux host.
This is the allocation logic:
...ANSWER
Answered 2019-Dec-25 at 19:44It looks like it is only mapping 10 pages (40 KB) in the EPT, but GUEST CR3 is 7776e0000, which is not mapped.
If you want to only map a small amount of memory into the guest, then all the guest structures need to be located within that guest physical address range.
QUESTION
trying to build ffmpeg on ubuntu 18.10
https://trac.ffmpeg.org/wiki/CompilationGuide/Ubuntu
first install dependencies
...ANSWER
Answered 2019-Feb-06 at 22:43nasm-2.13.03 has issues with gcc 8. The nasm instructions on the wiki has been updated to use nasm-2.14.02 (as of this answer) which will work for your gcc version.
So just reload the wiki page and try the nasm section again.
Alternatively, use the nasm package from the Ubuntu repo and skip the nasm section. You can do this because your distro is using a recent nasm. Users of older distros may have to compile, but I'm not sure what the minimum supported nasm is (but consider it to be ≥ 2.13 because that's what x264 requires).
QUESTION
I have worked out a toy hypervisor with VMX in Linux, and it can work well with my testing VM. Now I am trying to test suspend and resume my testing VM with my toy hypervisor. I did followings to suspend the VM.
The VM starts in real-mode, and then goes to protected mode. It call a wrmsr, which will cause VMEXIT. The hypervisor gets the VMEXIT, then saves the CPU contexts (gprs, segment regs, descriptor tables, etc) and the VM's memory into a disk file, and quit. (VMXON/VMCS regions are not cleared).
Now, restart the VM loader, it will read the disk file, save the CPU contexts into the VMCS fields, and populate the VM's memory. Then tell the hypervisor to start the VM by calling 'vmlaunch'. (Before that, the hypervisor will call vmxon, vmclear, vmptrld, and vmwrite the VMCS fields and guest CPU contexts). My expectation is the VM will resume from its RIP saved before.
But it failed with 'invalid guest state'
Below is the VMCS dump just at the WRMSR VMEXIT.
...ANSWER
Answered 2018-May-05 at 17:41FS ATTR and GS ATTR are invalid. See the checks on “Access-rights fields” in 26.3.1.2. If bit 16 is 0, then bits 7:0 must be non-zero, typically 0x93.
QUESTION
I'm currently working on automating a Win32 UI application that cannot be altered. So far my approach is using the standard message queue of the target application to inject my inputs. I've gotten quite far with that:
- "Clicking" buttons using
WM_COMMAND
works - Reading the names of tabs via
TCM_GETITEMA
and activating them via virtual mouse clicksWM_LBUTTONDOWN
/WM_LBUTTONUP
works - Reading enabled/disabled states of controls works
Where I'm stuck, however, is modifying the text of an editable ComboBox and its Edit control. I try using the WM_SETTEXT
message like so:
ANSWER
Answered 2018-Feb-02 at 21:14Yes, WM_SETTEXT
is a standard Windows message and the OS will take care of copying the data to the target process. You must pass a pointer which is valid in your own process.
QUESTION
Logically thinking, writes to any CPU stored variable should be faster than the respective memory operation, because there are no chances of a cache miss. These states are cached in the CPU, and they do not change any CPU state before the next VMLAUNCH/VMRESUME operation. Therefore, they should be faster than an equivalent operation on a memory address
This question arises when looking at different virtualization solutions provided by AMD and Intel. Intel has mandated that all changes to the VMCS data structure should always go through a VMREAD/VMWRITE interface and not through regular memory R/W operations. However, AMD does not pose any such restriction, and its VMCB region is modified by regular memory operations.
The gains in Intel approach should be faster VMExit/VMResume times vs AMD. However, Intel would loose out on the flexibility front with adding new instructions.
However, in reality, VMREAD/VMWRITE operations are slower than regular memory operations. This does not make any sense to me.
...ANSWER
Answered 2017-Oct-12 at 09:26Regular memory reads/writes are handled with dedicated hardware to optimize the hell out of them, because real programs are full of them.
Most workloads don't spend very much time on modifying special CPU control registers, so the internal handling of these instructions is often not heavily optimized. Internally, it may be microcoded (i.e. decodes to many uops from the microcode ROM).
Segment registers might not be a great analogy, because writing one triggers the CPU to load a descriptor from the GDT / LDT. But according to Agner Fog's testing for Nehalem, mov sr, r
has one per 13 cycle throughput, and decodes to 6 uops (from microcode). (He stopped testing segment register stuff for later CPUs.) Actually, I'm not sure if that's in 16-bit or 32-bit mode. If it's 16-bit real mode, then writing a segment register doesn't read a descriptor; it just updates the base and limit.
Reading a segment register is faster: one per clock. But that's still slower than reading a normal register (regular mov
instructions have 0.33c throughput on Nehalem).
Nehalem could only load and/or store once per clock, unlike Sandybridge-family which can do 2 loads per clock. But segment-register reads probably aren't faster.
Move to/from control registers might be even slower, because it's rarer than segment registers.
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