intel-cmt-cat | User space software for Intel Resource Director | Monitoring library
kandi X-RAY | intel-cmt-cat Summary
kandi X-RAY | intel-cmt-cat Summary
intel-cmt-cat is a C library typically used in Performance Management, Monitoring applications. intel-cmt-cat has no bugs, it has no vulnerabilities and it has low support. However intel-cmt-cat has a Non-SPDX License. You can download it from GitHub.
This software package provides basic support for Intel Resource Director Technology (Intel RDT) including: Cache Monitoring Technology (CMT), Memory Bandwidth Monitoring (MBM), Cache Allocation Technology (CAT), Code and Data Prioritization (CDP) and Memory Bandwidth Allocation (MBA). In principle, the software programs the technologies via Model Specific Registers (MSR) on a hardware thread basis. MSR access is arranged via a standard operating system driver: msr on Linux and cpuctl on FreeBSD. In the most common architectural implementations, presence of the technologies is detected via the CPUID instruction. In a limited number of special cases where CAT is not architecturally supported on a particular SKU (but instead a non-architectural (model-specific) implementation exists) it can be detected via brand string. This brand string is read from CPUID and compared to a table of known-supported SKUs. If needed, a final check is to probe the specific MSR’s to discover hardware capabilities, however it is recommended that CPUID enumeration should be used wherever possible. From software version v1.0.0 the library adds option to use Intel RDT via available OS interfaces (perf and resctrl on Linux). The library detects presence of these interfaces and allows to select the preferred one through a configuration option. As the result, existing tools like 'pqos' or 'rdtset' can also be used to manage Intel RDT in an OS compatible way. MSR interface remains the default option for now. 'pqos' tool wrappers have been added to help with the interface selection. 'pqos-os' and 'pqos-msr' for OS and MSR interface operations respectively. PID API compile time option has been removed and the APIs are always available. Note that proper operation of these APIs depends on availability and selection of OS interface. This software package is maintained, updated and developed on provides FAQ, usage examples and useful links. Please refer to INSTALL file for package installation instructions.
This software package provides basic support for Intel Resource Director Technology (Intel RDT) including: Cache Monitoring Technology (CMT), Memory Bandwidth Monitoring (MBM), Cache Allocation Technology (CAT), Code and Data Prioritization (CDP) and Memory Bandwidth Allocation (MBA). In principle, the software programs the technologies via Model Specific Registers (MSR) on a hardware thread basis. MSR access is arranged via a standard operating system driver: msr on Linux and cpuctl on FreeBSD. In the most common architectural implementations, presence of the technologies is detected via the CPUID instruction. In a limited number of special cases where CAT is not architecturally supported on a particular SKU (but instead a non-architectural (model-specific) implementation exists) it can be detected via brand string. This brand string is read from CPUID and compared to a table of known-supported SKUs. If needed, a final check is to probe the specific MSR’s to discover hardware capabilities, however it is recommended that CPUID enumeration should be used wherever possible. From software version v1.0.0 the library adds option to use Intel RDT via available OS interfaces (perf and resctrl on Linux). The library detects presence of these interfaces and allows to select the preferred one through a configuration option. As the result, existing tools like 'pqos' or 'rdtset' can also be used to manage Intel RDT in an OS compatible way. MSR interface remains the default option for now. 'pqos' tool wrappers have been added to help with the interface selection. 'pqos-os' and 'pqos-msr' for OS and MSR interface operations respectively. PID API compile time option has been removed and the APIs are always available. Note that proper operation of these APIs depends on availability and selection of OS interface. This software package is maintained, updated and developed on provides FAQ, usage examples and useful links. Please refer to INSTALL file for package installation instructions.
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intel-cmt-cat has a low active ecosystem.
It has 442 star(s) with 154 fork(s). There are 61 watchers for this library.
It had no major release in the last 12 months.
There are 5 open issues and 149 have been closed. On average issues are closed in 34 days. There are 2 open pull requests and 0 closed requests.
It has a neutral sentiment in the developer community.
The latest version of intel-cmt-cat is v4.2.0
Quality
intel-cmt-cat has no bugs reported.
Security
intel-cmt-cat has no vulnerabilities reported, and its dependent libraries have no vulnerabilities reported.
License
intel-cmt-cat has a Non-SPDX License.
Non-SPDX licenses can be open source with a non SPDX compliant license, or non open source licenses, and you need to review them closely before use.
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intel-cmt-cat releases are available to install and integrate.
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intel-cmt-cat Key Features
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intel-cmt-cat Examples and Code Snippets
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Community Discussions
Trending Discussions on intel-cmt-cat
QUESTION
lockf.c: No such file or directory
Asked 2020-Mar-14 at 23:18
Please see the UPDATE at the botton of this post for more info.
Below is the _pqos_api_lock program from cap.c from the Intel CMT-CAT distribution (cache management technology - cache allocation technology) at https://github.com/intel/intel-cmt-cat.
The function _pqos_api_lock calls lockf, which is defined in unistd.h, and unistd.h is included with the includes at the top of the file. However, debugging with gdb, I get "lockf.c: No such file or directory" at the line:
...ANSWER
Answered 2020-Mar-14 at 22:52I have unistd.h included, so why do I get this error?
You don't seem to understand the significance of this error (which is none). This error is safe to ignore, and doesn't affect your program's execution in any way.
The reason GDB displays this error is that GDB can't show you the source (because GDB doesn't know where that source is).
Chances are, you don't actually want to see this source at all.
I found source for lockf.c at https://code.woboq.org/userspace/glibc/io/lockf.c.html
Good. If you really want to see what locf does, you can look there.
perhaps I can link this into my executable
The function defined in lockf.c is already linked into your executable (you'd get a link error if it wasn't). You can't link source into your executable any more than you can link your kitchen sink into it.
What you can do is install libc6-dbg package, which includes source for all of GLIBC, and allows GDB to find the sources automatically.
Community Discussions, Code Snippets contain sources that include Stack Exchange Network
Vulnerabilities
No vulnerabilities reported
Install intel-cmt-cat
You can download it from GitHub.
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Table 1. Intel® RDT hardware support -------------------------------------------------------------------------------------------------------- | | CMT | MBM | L3 CAT | L3 CDP | L2 CAT | MBA | |--------------------------------------------------------------------------------------------------| |Intel® Xeon® processor E5 v3 | Yes | No | Yes (1)| No | No | No | |--------------------------------------------------------------------------------------------------| |Intel® Xeon® processor D | Yes | Yes | Yes (2)| No | No | No | |--------------------------------------------------------------------------------------------------| |Intel® Xeon® processor E3 v4 | No | No | Yes (3)| No | No | No | |--------------------------------------------------------------------------------------------------| |Intel® Xeon® processor E5 v4 | Yes | Yes | Yes (2)| Yes | No | No | |--------------------------------------------------------------------------------------------------| |Intel® Xeon® Scalable Processors (6) | Yes | Yes | Yes (2)| Yes | No | Yes (5)| |--------------------------------------------------------------------------------------------------| |Intel® Xeon® 2nd Generation Scalable Processors (7) | Yes | Yes | Yes (2)| Yes | No | Yes (5)| |--------------------------------------------------------------------------------------------------| |Intel® Atom® processor for Server C3000 | No | No | No | No | Yes (4)| No | --------------------------------------------------------------------------------------------------------. References: (1) Selected SKU’s only: Intel® Xeon® processor E5-2658 v3 Intel® Xeon® processor E5-2648L v3 Intel® Xeon® processor E5-2628L v3 Intel® Xeon® processor E5-2618L v3 Intel® Xeon® processor E5-2608L v3 Intel® Xeon® processor E5-2658A v3 Four L3 CAT classes of service (CLOS) and a set of pre-defined classes that should not be changed at run time. L3 CAT CLOS to hardware thread association can be changed at run time. (2) Sixteen L3 CAT classes of service (CLOS). There are no pre-defined classes of service and they can be changed at run time. L3 CAT CLOS to hardware thread association can be changed at run time. (3) Selected SKU’s only: Intel® Xeon® processor E3-1258L v4 Intel® Xeon® processor E3-1278L v4 Four L3 CAT classes of service (CLOS) and a set of pre-defined classes that should not be changed at run time. L3 CAT CLOS to hardware thread association can be changed at run time. (4) Four L2 CAT classes of service (CLOS) per L2 cluster. L2 CAT CLOS to hardware thread association can be changed at run time. (5) Eight MBA classes of service (CLOS). There are no pre-defined classes of service and they can be changed at run time. MBA CLOS to hardware thread association can be changed at run time. (6) Please find errata for Intel® Xeon® Processor Scalable Family at: https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-scalable-spec-update.pdf?asset=14615. (7) Please find errata for Second Generation Intel® Xeon® Scalable Processors at: https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/2nd-gen-xeon-scalable-spec-update.pdf. For additional Intel® RDT details please refer to the Intel® Architecture Software Development Manuals available at: http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html Specific information can be found in volume 3, Chapters 17.18 and 17.19 (revision 064).
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