cortex | A fault-tolerant events/alerts correlation engine | Monitoring library

I want to implement an embedded project using stm32F0 (arm-based) with VS Code. The project ran properly on other systems.

1. I Added C/C++ extension to visual studio
2. I installed a compiler for cortex-m0 arm: GNU Arm Embedded toolchain/gcc arm for windows.
3. Makefiles installed: binaries file + dependencies file
4. openOCD installed (open On Chip Debugger)
5. tasks.json (build instructions), c_cpp_properties.json (compiler path and IntelliSense settings) were created. I modified the Include path because my program includes header files that aren't in my workspace, and that is not in the standard library path.

c_cpp_properties.json file

I have a huge memory block (bit-vector) with size N bits within one memory page, consider N on average is 5000, i.e. 5k bits to store some flags information.
At a certain points in time (super-frequent - critical) I need to find the first bit set in this whole big bit-vector. Now I do it per-64-word, i.e. with help of __builtin_ctzll). But when N grows and search algorithm cannot be improved, there can be some possibility to scale this search through the expansion of memory access width. This is the main problem in a few words

There is a single assembly instruction called BSF that gives the position of the highest set bit (GCC's __builtin_ctzll()). So in x86-64 arch I can find the highest bit set cheaply in 64-bit words.

But what about scaling through memory width?
E.g. is there a way to do it efficiently with 128 / 256 / 512 -bit registers?
Basically I'm interested in some C API function to achieve this, but also want to know what this method is based on.

UPD: As for CPU, I'm interested for this optimization to support the following CPU lineups:
Intel Xeon E3-12XX, Intel Xeon E5-22XX/26XX/E56XX, Intel Core i3-5XX/4XXX/8XXX, Intel Core i5-7XX, Intel Celeron G18XX/G49XX (optional for Intel Atom N2600, Intel Celeron N2807, Cortex-A53/72)

P.S. In mentioned algorithm before the final bit scan I need to sum k (in average 20-40) N-bit vectors with CPU AND (the AND result is just a preparatory stage for the bit-scan). This is also desirable to do with memory width scaling (i.e. more efficiently than per 64bit-word AND)

Read also: Find first set

I'm writing Assembly using Thumb for a Cortex-M7.

I would like to know what would be a good approach, from a software design standpoint, to a situation where each derived class should have a different type of polymorphic data member. In more detail:

I'm writing a library that has an abstract base class Base that users of the library will inherit from. for one member of Base, let's call it BaseMember, I want polymorphic behavior. What I mean by that is that various classes derived from Base will "contain" different subclasses of BaseMember - some will contain a OneDerivedMember, others will contain AnotherDerivedMember etc (all of these are derived from BaseMember, and all are supplied in the library). The reason for wanting that, is that I want to be able to go over some collection of Base pointers and activate some functionality of BaseMember (which is implemented differently for its different derived classes). As I understand it, I am guessing I have to make BaseMember a pointer. Now my questions start:

1. First of all, is all of this even a good approach or do you sense a "code smell" here? Is building it like that a common practice?

Assuming the basic approach is OK:

1. Where would be the proper location to allocate the BaseMember pointer? in the constructors of the various derived classes?

2. Can I enforce that the derived classes actually do this allocation? i.e. what if a user didn't understand, or forget, that they needed to allocate one kind or other of SomeDerivedMember and make the BaseMember pointer point to it? How can I force it not to compile in such a case?

3. Where should this member be released (de-allocated)? I suppose the RAII approach dictates it would be in the same scope it was allocated in (so, destructor of derived class?) but this forces every user of the library to remember to do this de-allocation. Instead, I could do it in the destructor of Base (i.e. in the library, not by the user) - but would this violate the RAII principle? and what if the user DID decide to de-allocate it (double delete...)?

4. Alternatively to all this, can you imagine a way to have equivalent polymorphic behavior without even using dynamic allocation? This code is for a low-level embedded MCU, Cortex M4 or similar cores and bare metal (no OS) - so I try to stay away from dynamic allocation wherever possible.

I feel this kind of situation must be be fairly common, and there would be a design pattern that solves this cleanly, however I'm not sure what that would be.

Example code:

I'm currently trying to learn Rust (for embedded specifically), coming from a background of C for embedded systems and Python. So far, I've been reading Rust Programming Language and Rust for Embedded, and read a few blog posts on the web.

I want my first project to be a simple "Blinky", where an LED blinks infinitely. I've got an STM32L152CDISCOVERY board with an STM32L152 chip in it (basically same as STM32L151), which is a Cortex M3.

Instead of implementing everything from scratch, I want to leverage existing crates and HALs. I've found two that seem promising: stm32l1 and stm32l1xx-hal. I've tried to read the documentation of each of them and also part of the source code, but I still can't figure out how to use them correctly.

Got a few questions about Rust and about the crates:

1. I see that stm32l1xx-hal has a dependency on stm32l1. Do I need to add both as a dependency in my Cargo.toml file? Or will that create problems related to ownership?

2. Is this the correct way to add them? Why is the second one added like that [dependencies.stm32l1]?

   ...

I cannot pass Story #5: "When I click a .nav-link button in the nav element, I am taken to the corresponding section of the landing page." I have all of my href attributes set to the corresponding id attributes and when i click on them they take me to the correct section of the page, but I am still failing this test... What am I Doing Wrong???

The code I wrote is below:

I wrote the following code to program a STM32F439 microcontroller based on the ARM Cortex-M4 processor core. I defined a timer interrupt handler that is triggered every time when TIM7 counts to the end of 1 second so that it executes a specified piece of code every second. The contents of functions InitRCC() (which initialises RCC to enable GPIOs) and ConfGPIO() (which configures GPIO pins) are omitted.

I am using qemu-arm and the ARM Workbench IDE to run/profile an ARM binary which was built with armcc/armlink (an .axf-File, program written in C). This works fine with Cortex-A9 and ARM926/ARM5TE. However, whatever I tried, it doesnt work when the binary is built for Cortex-M4. Both the simulator and qemu-arm hang when M4 is selected as CPU.

I know that this processor requires some additional startup code, but I could find any comprehensive tutorial on how to get it running. Does anyone know how to do this? I have a quite big project with one main function, but it would already help if a "hello world" or some simple program which takes arguments would run.

Here is the command line I am using with Cortex-A9:

Note: Although question is duplicate, but current answers lacks details, so I wanted to post another one.

I'm using C++Builder developed by Embarcadero.

For Windows, it compiles fine.

For Android, it shows the following error: