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QUESTION
as you can see in the image, on clicking on Men the list of categories are shown. What I want is to add a transition or animate the increasing height. Also I want to rotate the arrow smoothly on showing the category list. Thanks.
here is the code of my component and also I have pasted the dummy data for the component.
...ANSWER
Answered 2021-May-03 at 11:52QUESTION
I am trying to build a 4-bit counter in system Verilog using logical elements only. I am using simple D-flipflops with some XOR and AND logic to achieve this. However, while simulating, the Output values are constantly 0, and I am not sure what's the issue.
Code:
...ANSWER
Answered 2021-Mar-03 at 13:52When I try to compile your code, I get errors with multiple simulators.
In the testbench, the out0 signal has multiple drivers. The same for the other 3 "out" signals. Since they are outputs of the design, you should not make assignments to them in the testbench. Also you should declare them as wire, not reg. Here is the modified testbench:
QUESTION
Details for the stateful behaviour for operators such as match (ie. m//g), stat (ie. stat _) and range (ie. //..//) are in the documentation. However is there a 'listing' of all operators or functions that exhibit stateful behaviour? The ones that come to mind are:
ANSWER
Answered 2021-Jan-11 at 00:44There are three stateful operators.
globin scalar context (including<>used asglob).
QUESTION
I have the following code where as of now, we have clothes, and footwear. But in future there can be many more item Object types. The class Foo is templated with Object and its member functions here are the same for both eClothes and eFootwear, but things are templated further in actual code.
Is there a way to deduplicate the implementation of method order ? Since there's a one to one mapping from
- Object::clothes -> eClothes
- Object::footwear -> eFootwear
.. Is there some technique that I can use to fix the template parameter of order based on type ? So that one class instantiation accepts orders of its corresponding kind only, otherwise it's a compile time error ?
ANSWER
Answered 2020-Dec-11 at 08:16Define traits that maps Object to its value type. Like:
QUESTION
I have a problem in the test bench code, and I am not getting correct waveforms. Even the clock does not trigger.
CODE for D Flipflop:
...ANSWER
Answered 2020-Jul-22 at 19:38Here is what happens in the always block in your testbench.
At time 0, clk and D are 0.
At time 20, you invert clk, which becomes 1.
At time 55, you invert D, which becomes 1.
At time 5055, you call $finish which terminates the simulation. The statements in the block only execute once, which is why your inputs never change more than once.
In your testbench, initialize them as 0 in an initial block, then separate the clock generation from the data signal.
QUESTION
I am getting an error when trying to move my repository initiation from my Application class to a config class. It seems strange because the urlRepository.save call does not throw, while the urlRepository.findAll() gets a null. What am I doing wrong here?
Before (Works Fine - prints to console with the preloaded URL) ...ANSWER
Answered 2020-Jun-14 at 20:36MongoUrlRepository supposed to be an interface, that's the way Spring could manage it's crud implementations automatically. Since you are declaring it as a class you basically overriding the builtin finder methods to just return null, that's where your NPE is coming from.
see the examples from spring.io: https://spring.io/guides/gs/accessing-data-mongodb/
Why it worked in the 1st case:
QUESTION
It is async reset. D flipflop when i change reset from one to zero, it doesn't immediately raise the output from zero to one. but when i add in @always ( posedge clk or posedge reset or negedge reset ) it immediately change
Verilog: ...ANSWER
Answered 2019-Aug-28 at 14:39It does exactly what you tell it to do: mimic a flip-flop with an asynchronous active-high reset. The following line from your code
QUESTION
I'm trying to design a 64-bit Shift register in Verilog HDL but when I test the code with a testbench, all the bits are zeros. I don't know where I'm going wrong. Here is my code and the test bench result:
...ANSWER
Answered 2020-Apr-24 at 18:06Here ff[0] <= shift_in;, you are trying to assign a 64-bit variable to 1-bit variable. Since you use a even number (64'd34645767785344) for shift_in in your testbench, its LSB is 0. Therefore, you keep inserting 0 to ff.
Make your shift_in input 1-bit and change your testbench such that you will give 1-bit at a time as input.
QUESTION
I'm Trying to make a 64-bit shift register in Verilog HDL. When I try the code in the testbench, I just get xxxxxx as the output till all the bits have been shifted. I don't know what the problem is. Here Is my code with the testbench and the result:
...ANSWER
Answered 2020-Apr-24 at 16:40You declare ff as a reg, and the default value of a reg is x. Before the 1st posedge of the clock, all 64 bits of ff are x (unknown). After the 1st posedge of the clock, ff[0] becomes 0 because shift_in[0] is 0. And so on, until you reach 64 clocks, then all ff bits are 0. shift_out just follows ff.
Typically, your design would also have a reset signal. If you had one, you could assert reset at the start, and assign ff to 0 during reset. Here is what is looks like with a reset:
QUESTION
Class ShoeList
...ANSWER
Answered 2020-Apr-14 at 03:17In your Shoe class you have one constructor with 4 parameters.
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