nop | javascript function that does nothing ; it 's like super

Your gadget is at 0x55555558f8.

Ropper shows the addresses of gadgets the way the ELF header describes the memory layout of the binary. According to that header:

• The file contents 0x0-0xadc are to be mapped as r-x at address 0x0.
• The file contents 0xdb8-0x1048 are to be mapped as rw- at address 0x10db8.

Account for page boundaries and you get one page mapping file offset 0x0 to address 0x0 as executable and two pages mapping file offset 0x0 to address 0x10000 as writeable.

From your GDB dump, these mappings are created at 0x5555555000 and 0x5555565000 in the live process, respectively.

So, apparently the problem lies with windows, or the WSL to be precise. WSL does not seem to support the set termguicolors which is responsible for the weird colors appearing on screen. And because this is essential for several colorschemes (otherwise they look very different). So unless WSL2 provides this feature I don't think it is possible for windows to have any of the fancy colorschemes. The best option is to probably use a virtual machine and run linux or dual-boot your device.

I fixed it by myself. The management interface itself was missing a route to the VLAN2 net. Works now :)

The slow version:

Note that the sub rax, 1 \ jne pair goes right across the boundary of the ..80 (which is a 32byte boundary). This is one of the cases mentioned in Intels document regarding this issue namely as this diagram:

So this op/branch pair is affected by the fix for the JCC erratum (which would cause it to not be cached in the µop cache). I'm not sure if that is the reason, there are other things at play too, but it's a thing.

In the fast version, the branch is not "touching" a 32byte boundary, so it is not affected.

There may be other effects that apply. Still due to crossing a 32byte boundary, in the slow case the loop is spread across 2 chunks in the µop cache, even without the fix for JCC erratum that may cause it to run at 2 cycles per iteration if the loop cannot execute from the Loop Stream Detector (which is disabled on some processors by an other fix for an other erratum, SKL150). See eg this answer about loop performance.

To address the various comments saying they cannot reproduce this, yes there are various ways that could happen:

• Whichever effect was responsible for the slowdown, it is likely caused by the exact placement of the op/branch pair across a 32byte boundary, which happened by pure accident. Compiling from source is unlikely to reproduce the same circumstances, unless you use the same compiler with the same setup as was used by the original poster.
• Even using the same binary, regardless of which of the effects is responsible, the weird effect would only happen on particular processors.

Your first stops for further reading should probably be:

• What Every Programmer Should Know About Memory? re: cache
• https://agner.org/optimize/ re: everything else about writing efficient asm.
• https://uops.info/ for a better version of Agner Fog's instruction tables.
• See also other links in https://stackoverflow.com/tags/x86/info

so I will put out microoptimalisation until it will suffer performance problems and then I will start with profiling.

Yes, probably good to start trying stuff so you have something to profile with HW performance counters, so you can correlate what you're reading about performance stuff with what actually happens. And so you get some ideas of possible details you hadn't thought of yet before you go too far into optimizing your overall design idea. You can learn a lot about asm micro-optimization by starting with something very small scale, like a single loop somewhere without any complicated branching.

Since modern CPUs use split L1i and L1d caches and first-level TLBs, it's not a good idea to place code and data next to each other. (Especially not read-write data; self-modifying code is handled by flushing the whole pipeline on any store too near any code that's in-flight anywhere in the pipeline.)

Related: Why do Compilers put data inside .text(code) section of the PE and ELF files and how does the CPU distinguish between data and code? - they don't, only obfuscated x86 programs do that. (ARM code does sometimes mix code/data because PC-relative loads have limited range on ARM.)

Yes, making sure all your data allocations are nearby should be good for TLB locality. Hardware normally uses a pseudo-LRU allocation/eviction algorithm which generally does a good job at keeping hot data in cache, and it's generally not worth trying to manually clflushopt anything to help it. Software prefetch is also rarely useful, especially in linear traversal of arrays. It can sometimes be worth it if you know where you'll want to access quite a few instructions later, but the CPU couldn't predict that easily.

AMD's L3 cache may use adaptive replacement like Intel does, to try to keep more lines that get reused, not letting them get evicted as easily by lines that tend not to get reused. But Zen2's 512kiB L2 is relatively big by Forth standards; you probably won't have a significant amount of L2 cache misses. (And out-of-order exec can do a lot to hide L1 miss / L2 hit. And even hide some of the latency of an L3 hit.) Contemporary Intel CPUs typically use 256k L2 caches; if you're cache-blocking for generic modern x86, 128kiB is a good choice of block size to assume you can write and then loop over again while getting L2 hits.

The L1i and L1d caches (32k each), and even uop cache (up to 4096 uops, about 1 or 2 per instruction), on a modern x86 like Zen2 (https://en.wikichip.org/wiki/amd/microarchitectures/zen_2#Architecture) or Skylake, are pretty large compared to a Forth implementation; probably everything will hit in L1 cache most of the time, and certainly L2. Yes, code locality is generally good, but with more L2 cache than the whole memory of a typical 6502, you really don't have much to worry about :P

Of more concern for an interpreter is branch prediction, but fortunately Zen2 (and Intel since Haswell) have TAGE predictors that do well at learning patterns of indirect branches even with one "grand central dispatch" branch: Branch Prediction and the Performance of Interpreters - Don’t Trust Folklore

You don't need to specify an operand size for the memory operand,
just use movdqu xmm0, [rsi] and let xmm0 imply 128-bit operand-size.
NASM supports SSE/AVX/AVX-512 instructions.

If you did want to specify an operand-size, the name for 128-bit is oword, according to ndisasm if you assemble that instruction and then disassemble the resulting machine code. oword = oct-word = 8x 2-byte words = 16 bytes.

• What are the sizes of tword, oword and yword operands?
• What comes after QWORD?

Note that GNU .intel_syntax noprefix (as used by objdump -drwC -Mintel) will use xmmword ptr, unlike NASM.

If you really want to use xmmword, %define xmmword oword at the top of your file.

The operand-size is always implied by the mnemonic and / or other register operands for all SSE/AVX/AVX-512 instructions; I can't think of any instructions where you need to specify qword vs. oword vs. yword or anything, the way you do with movsx eax, byte [rdi] vs. word [rdi]. Often it's the same size as the register, but there are exceptions with some shuffle / insert / extract instructions. For example:

• SSE2 pinsrw xmm0, [rdi], 3 loads a word and merges it into bytes 6 and 7 of xmm0.
• SSE2 movq [rdi], xmm0 stores the qword low half
• SSE1 movhps [rdi], xmm0 stores the high qword
• AVX1 vextractf128 [rdi], ymm0, 1 does a 128-bit store of the high half
• AVX2 vpmovzxbw ymm0, [rdi] does packed byte->word zero extension from a 128-bit memory source operand
• AVX-512F vpmovdb [rdi]{k1}, zmm2 narrows dword to byte elements (with truncation; other versions do saturation) and does a 128-bit store, with masking at byte granularity. (One of the only ways to do byte-granularity masking without AVX-512BW, other than legacy-SSE maskmovdqu which has cache-evicting NT semantics. So I guess that makes it especially interesting for Xeon Phi KNL.)

You could specify oword on any of those to make sure the size of the memory access is what you think it is. (i.e. to have NASM check it for you.)

mul al multiplies AL by AL and puts the result in AX. Since you set AL to 10h, the result is AX=100h and then you store AL which is zero. If you want to multiply AL by AH and store the result you should do this:

May 19, 2021 upgrade JUnit with 5.7.2_1 still get:

Never include core_cm4.h or stm32f439xx.h directly.

You need to define the correct part number macro STM32F439xx using a command line flag eg: -DSTM32F439xx.

After that you should only include "stm32f4xx.h". This will include the correct CMSIS headers which define _enable_irq and _disable_irq and all the valid IRQ numbers for the part.

Regarding TIM7_DAC_IRQn, this is incorrect. The DAC shares an interrupt with TIM6, and TIM7 has its own separate one. Chose either TIM6_DAC_IRQn or TIM7_IRQn.