cache-simulator | A processor cache simulator for the MIPS architecture

by caleb531 Python Version: 2.0.1 License: MIT

X-Ray Key Features Code Snippets(2)Community Discussions(1)Vulnerabilities Install Support

kandi X-RAY | cache-simulator Summary

cache-simulator is a Python library. cache-simulator has no bugs, it has no vulnerabilities, it has build file available, it has a Permissive License and it has low support. You can install using 'pip install cache-simulator' or download it from GitHub, PyPI.

This program simulates a processor cache for the MIPS instruction set architecture. It can simulate all three fundamental caching schemes: direct-mapped, n-way set associative, and fully associative. The program must be run from the command line and requires Python 3.4+ to run. Executing the program will run the simulation and print an ASCII table containing the details for each supplied word address, as well as the final contents of the cache. For example, the following command simulates a 3-way set associative LRU cache, with 2 words per block. To see all examples and their respective outputs, see examples.txt.

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Support

cache-simulator has a low active ecosystem.

It has 22 star(s) with 11 fork(s). There are 1 watchers for this library.

It had no major release in the last 12 months.

cache-simulator has no issues reported. There are no pull requests.

It has a neutral sentiment in the developer community.

The latest version of cache-simulator is 2.0.1

Quality

cache-simulator has 0 bugs and 0 code smells.

Security

cache-simulator has no vulnerabilities reported, and its dependent libraries have no vulnerabilities reported.

cache-simulator code analysis shows 0 unresolved vulnerabilities.

There are 0 security hotspots that need review.

License

cache-simulator is licensed under the MIT License. This license is Permissive.

Permissive licenses have the least restrictions, and you can use them in most projects.

Reuse

cache-simulator releases are available to install and integrate.

Deployable package is available in PyPI.

Build file is available. You can build the component from source.

Installation instructions are not available. Examples and code snippets are available.

cache-simulator saves you 322 person hours of effort in developing the same functionality from scratch.

It has 773 lines of code, 76 functions and 15 files.

It has medium code complexity. Code complexity directly impacts maintainability of the code.

Top functions reviewed by kandi - BETA

kandi has reviewed cache-simulator and discovered the below as its top functions. This is intended to give you an instant insight into cache-simulator implemented functionality, and help decide if they suit your requirements.

Runs the simulation
Display the address references
Prints the given cache
Read references
Checks if the given address is hit
Replace a block in the cache
Replaces the entry with the given replacement policy
Mark the address as last seen
Return a cache entry
Given a list of word addresses return a list of Reference objects
Returns a list of all consecutive consecutive words
Parse command line arguments
Returns the long description

Get all kandi verified functions for this library.

cache-simulator Key Features

No Key Features are available at this moment for cache-simulator.

cache-simulator Examples and Code Snippets

Cache Simulator

Python

Lines of Code : 22

License : Permissive (MIT)

Copy

# 3-way set associative (LRU; 2 words per block)
cache-simulator --cache-size 24 --num-blocks-per-set 3 --num-words-per-block 2 --word-addrs 3 180 43 2 191 88 190 14 181 44 186 253

     WordAddr      BinAddr          Tag        Index       Offset

Cache Simulator,Installing

Python

Lines of Code : 1

License : Permissive (MIT)

Copy

pip install cache-simulator

Community Discussions

Trending Discussions on cache-simulator

Cannot use IARG_MEMORYREAD_SIZE on non-standard memory access of instruction at 0x7ffbdcbe4e88: xsave ptr [rsp+0x40]

QUESTION

Cannot use IARG_MEMORYREAD_SIZE on non-standard memory access of instruction at 0x7ffbdcbe4e88: xsave ptr [rsp+0x40]

Asked 2019-May-07 at 22:49

I'm trying to use Intel Pin for investigating memory activity of an executable. And I tried to use IARG_MEMORYREAD_SIZE parameter. Here is the source code.

...

ANSWER

Answered 2019-May-07 at 22:49

This might fall under the case where you need to use IARG_MULTI_MEMORYACCESS_EA (see the documentation).

Basically, according to the XSAVE documentation the number of bytes written to the memory pointed by the instruction is not constant and depends on the following factors:

The requested-feature bitmap (RFBM)
The logical-AND of EDX:EAX
The logical-OR of XCR0 with the IA32_XSS MSR

You can check if you can use IARG_MEMORYREAD_SIZE (constant memory sized instruction) or not with INS_hasKnownMemorySize.

Source https://stackoverflow.com/questions/55992337

Community Discussions, Code Snippets contain sources that include Stack Exchange Network

Vulnerabilities

No vulnerabilities reported

Install cache-simulator

You can install using 'pip install cache-simulator' or download it from GitHub, PyPI.
You can use cache-simulator like any standard Python library. You will need to make sure that you have a development environment consisting of a Python distribution including header files, a compiler, pip, and git installed. Make sure that your pip, setuptools, and wheel are up to date. When using pip it is generally recommended to install packages in a virtual environment to avoid changes to the system.

Support

For any new features, suggestions and bugs create an issue on GitHub. If you have any questions check and ask questions on community page Stack Overflow .

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