Coherence | DLNA/UPnP Media Server and Framework for the Digital Living | Video Utils library

Let me frame this by saying I don't think there's an "authoritative" answer to this question. That said, you've provided enough constraints that a suggested path is at least worthwhile. Let's review the requirements:

• Solution must use std::vector. This is in my opinion the most unfortunate requirement for reasons I won't get into here.
• Solution must be standards compliant and not resort to rule violations, like the strict aliasing rule.
• Solution must either reduce the number of allocations performed, or reduce the overhead of allocations to the point of being negligible.

In my opinion this is definitely a job for a custom allocator. There are a couple of off-the-shelf options that come close to doing what you want, for example the Boost Pool Allocators. The one you're most interested in is boost::pool_allocator. This allocator will create a singleton "pool" for each distinct object size (note: not object type), which grows as needed, but never shrinks until you explicitly purge it.

The main difference between this and your solution is that you'll have distinct pools of memory for objects of different sizes, which means it will use more memory than your posted solution, but in my opinion this is a reasonable trade-off. To be maximally efficient, you could simply start a batch of operations by creating vectors of each needed type with an appropriate size. All subsequent vector operations which use these allocators will do trivial O(1) allocations and deallocations. Roughly in pseudo-code:

It's hard to help since the blog you reference to is in Chinese. Still, I've noticed that the first figure seems to show a multi-socket architecture. So I made a few experiments.

a) my PC, Intel(R) Core(TM) i7-2600K CPU @ 3.40GHz, single socket, two cores, two threeds per core:

0:

I think you have a fundamental misunderstanding of cache blocking, misunderstood what you were being asked to do, or whoever asked you to do it doesn't understand. I am also hesitant to give you the full answer because this smells of a contrived example for a home work problem.

The idea is to block/tile/window up the data you're operating on, so the data you're operating on stays in the cache as you operate on it. To do this effectively you need to know the size of the cache and the size of the objects. You didn't give us enough details to know these answers but I can make some assumptions to illustrate how you might do this with the above code.

First how arrays are laid out in memory just so we can reference it later. Say dimension is 3.

That means we have a grid layout where i is the first number and j is the second like...

check out the following scripts [with comm.Barrier for sync. communication]. In the script, I've written and read the files as a chunk of h5py dataset which is memory efficient.

Yes, I think we can prove that a == 1 || b == 1 is always true. Most of the ideas here were worked out in comments by zwhconst and Peter Cordes, so I just thought I would write it up as an exercise.

(Note that X, Y, A, B below are used as the dummy variables in the standard's axioms, and may change from line to line. They do not coincide with the labels in your code.)

Suppose b = x.load() in thread2 yields 0.

We do have the coherence ordering that you asked about. Specifically, if b = x.load yields 0, then I claim that x.load() in thread2 is coherence ordered before x.store(1) in thread1, thanks to the third bullet in the definition of coherence ordering. For let A be x.load(), B be x.store(1), and X be the initialization x{0} (see below for quibble). Clearly X precedes B in the modification order of x, since X happens-before B (synchronization occurs when the thread is started), and if b == 0 then A has read the value stored by X.

(There is possibly a gap here: initialization of an atomic object is not an atomic operation (3.18.1p3), so as worded, the coherence ordering does not apply to it. I have to believe it was intended to apply here, though. Anyway, we could dodge the issue by putting x.store(0, std::memory_order_relaxed); in main before starting the threads, which would still address the spirit of your question.)

Now in the definition of the ordering S, apply the second bullet with A = x.load() and B = x.store(1) as before, and Y being the atomic_thread_fence in thread1. Then A is coherence-ordered before B, as we just showed; A is seq_cst; and B happens-before Y by sequencing. So therefore A = x.load() precedes Y = fence in the order S.

Now suppose a = y.load() in thread1 also yields 0.

By a similar argument to before, y.load() is coherence ordered before y.store(1), and they are both seq_cst, so y.load() precedes y.store(1) in S. Also, y.store(1) precedes x.load() in S by sequencing, and likewise atomic_thread_fence precedes y.load() in S. We therefore have in S:

• x.load precedes fence precedes y.load precedes y.store precedes x.load

which is a cycle, contradicting the strict ordering of S.

The error message

The fitting is difficult due to the high level of scatter.

A significantly better fitting is obtained in adding the parameter C in the equation.

IN ADDITION in order to answer to some comments :

The method leading to the above result consists in two steps.

First step : a non-conventional method which is not iterative an doesn't requires initial "guessed" values of the parameters. The general principle is explained in this paper : https://fr.scribd.com/doc/14674814/Regressions-et-equations-integrales

Since the case of the function y(x)=(A * cos(K * x) + C) * exp(-B * x) is not explicitly treated in the paper the application to this function is given below :

It is not rare that people not familiar with this method make mistake in coding and say that the calculus fails. A lot of time is lost in discussions before the mistake be found and corrected. In order to avoid wasting time a "test" sheet is provided below. With the very small data it is easy for the user to check his code in comparing each intermediate numerical value to the correct values.

Then the method can be used with the big data given by the OP. The result is :

Don't be surprised that the values of the parameters are not exactly the same as the values given on the first figure at begining of my answer. This is because the criteria of fitting is not the same.

In his question the OP doesn't specify a criteria of fitting (LMSE, or LMAE, or LMSRE, or etc.). To each criteria of fitting correspond a different result. When the scatter is large the results can be very different one to the others. Since the scatter is very large in the present case, one cannot avoid to chose a particular criteria of fitting. If not the result is not unique. That is why a second step is necessary in the present case. But this not a general necessity.

Second step (Eventually):

We have to chose a criteria of fitting. For example Least Mean Square Errors.

A non-linear method of regression (in which the chosen criteria is implemented) must be used. They is a lot of software. The calculus is iterative and one have to give some "guessed" initial values to start the iteration.

In case of large scatter the convergence is not always good. The result might be far to be good with eventually failure if the initial values are not close to the correct values which are unknown. This is (partially) avoid thanks to the above first step. One can use the above values of K,B,A,C as rather good initial values. That is what was done to compute the values written on the first figure in my answer. This explains why the first figure is different from the last one.

NOTE :

To be honest one must acknowledge that the above method isn't infallible, especially in case of large scatter. I am surprized that a not too bad result be obtained. With three numerical integrations I was expecting much more difficulty. Certainly the large number of points is favourable. May be we are lucky with this data. We could have worse results with other set of data.

The acquire and release semantics required for C++11 std::mutex (and equivalents in other languages, and earlier stuff like pthread_mutex) would be very expensive to implement if you didn't have coherent cache. You'd have to write-back every dirty line every time you released a lock, and evict every clean line every time you acquired a lock, if couldn't count on the hardware to make your stores visible, and to make your loads not take stale data from a private cache.

But with cache coherency, acquire and release are just a matter of ordering this core's accesses to its own private cache which is part of the same coherency domain as the L1d caches of other cores. So they're local operations and pretty cheap, not even needing to drain the store buffer. The cost of a mutex is just in the atomic RMW operation it needs to do, and of course in cache misses if the last core to own the mutex wasn't this one.

C11 and C++11 added stdatomic and std::atomic respectively, which make it well-defined to access shared _Atomic int variables, so it's not true that higher level languages don't expose this. It would hypothetically be possible to implement on a machine that required explicit flushes/invalidates to make stores visible to other cores, but that would be very slow. The language model assumes coherent caches, not providing explicit flushes of ranges but instead having release operations that make every older store visible to other threads that do an acquire load that syncs-with the release store in this thread. (See When to use volatile with multi threading? for some discussion, although that answer is mainly debunking the misconception that caches could have stale data, from people mixed up by the fact that the compiler can "cache" non-atomic non-volatile values in registers.)

In fact, some of the guarantees on C++ atomic are actually described by the standard as exposing HW coherence guarantees to software, like "write-read coherence" and so on, ending with the note:

http://eel.is/c++draft/intro.races#19

[ Note: The four preceding coherence requirements effectively disallow compiler reordering of atomic operations to a single object, even if both operations are relaxed loads. This effectively makes the cache coherence guarantee provided by most hardware available to C++ atomic operations. — end note

(Long before C11 and C++11, SMP kernels and some user-space multithreaded programs were hand-rolling atomic operations, using the same hardware support that C11 and C++11 finally exposed in a portable way.)

Also, as pointed out in comments, coherent cache is essential for writes to different parts of the same line by other cores to not step on each other.

ISO C11 guarantees that a char arr[16] can have arr[0] written by one thread while another writes arr[1]. If those are both in the same cache line, and two conflicting dirty copies of the line exist, only one can "win" and be written back. C++ memory model and race conditions on char arrays

ISO C effectively requires char to be as large as smallest unit you can write without disturbing surrounding bytes. On almost all machines (not early Alpha and not some DSPs), that's a single byte, even if a byte store might take an extra cycle to commit to L1d cache vs. an aligned word on some non-x86 ISAs.

The language didn't officially require this until C11, but that just standardized what "everyone knew" the only sane choice had to be, i.e. how compilers and hardware already worked.

The error

impl for a type outside of the crate where the type is defined

Is because I left off for MyString in impl ... for MyString {}. An easy syntax error to make that can be fixed by adding that,