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As it turns out, all the ATA commands need to be in 8 bit (or 1 byte) input/output. This means that all the inw() and outw() function calls should be converted into inb() and outb() function calls instead. When I made the switch, the problems disappeared!

You can find this information using dmidecode:

Firmware (e.g. OVMF) uses chipset specific methods to determine the IO port of the ACPI timer; and then constructs the FADT and fills it in so that an OS doesn't need to be chipset specific.

If you don't want to use FADT, then you can write a chipset specific driver for each chipset. For some cases (open source emulators) this may be relatively easy, and for some cases (proprietary and undocumented real hardware) this will be almost impossible.

So I figured out my problem!

I missed a . in a symbol name.

Given the outb macro definition, NASM will expand your outb [com1+1], 0x00 macro invokation into:

everything was right but the gdt wasn't initialized the right way

As Michael Petch explained in the comments, you don't need a TSS if the interrupt handler is executing at the same privilege.

The CPU will read the necessary SS:SP pair from the TSS only if the interrupt is going to be executed in a more privileged ring w.r.t the current code's ring (e.g. a transition from ring 3 to ring 0).
This is detailed in chapter 6.12.1 of the 3rd Intel's manual:

When the processor performs a call to the exception- or interrupt-handler procedure:

• If the handler procedure is going to be executed at a numerically lower privilege level, a stack switch occurs. When the stack switch occurs:
  -. The segment selector and stack pointer for the stack to be used by the handler are obtained from the TSS for the currently executing task. On this new stack, the processor pushes the stack segment selector and stack pointer of the interrupted procedure.
  [redacted]

• If the handler procedure is going to be executed at the same privilege level as the interrupted procedure: a. The processor saves the current state of the EFLAGS, CS, and EIP registers on the current stack (see Figure 6-4).
  [redacted]

It's worth noting that in 64-bit mode the task switching mechanism is no longer supported.
We cannot call or jmp or use a task gate.
However, confusingly enough, the TSS is still used and mandatory. This structure is now used as it has been used in practice by the mainstream OSes: as a global (read: the same for every task, at least in theory) buffer where to store stack switching and other information.
Also worth noting is that in 64-bit mode the new IST mechanism is used for task switching (see section 6.14.5 of the 3rd Intel's manual).

How can it work if I don’t have this TSS ? Is it because when interrupts occurs the CPU will still automatically push EIP, CS, EFLAGS, EPS, SS and restore them on iret ?

The CPU won't use the TSS when there is no privilege level change. To understand what is pushed and in what order, see this picture below taken from Intel's manual volume 3:

If I load a single TSS, how this interrupt will know that it should use this TSS ? With ltr instruction that will take the according tss segment inside the GDT?

When an interrupt occurs and the CPU realizes that a privilege change is going to happen it will read the tr register to reach the current TSS.
Since loading the tr is a privilege operation, the OS is in control of what TSS will be used.
Infact, if the OS wanted to use two different TSS, A and B, for two different programs Pa and Pb, it will reload tr each time is about to execute one of those programs.

So yes, the ltr instruction is how the OS controls the TSS currently active.

Not really related, but when using hardware context switching and jmp to one TSS, will it automatically jump to the previous (no next field so I’m a little bit lost) tss segment automatically when return ?

A task switching, when supported, can be invoked with: jmp, call, int, an interrupt, or an exception.
All of these methods but jmp will link the current task (the one being switched out) to the new task (the one being switched in).
This is achieved through the Previous Task Link field in the TSS, the new TSS will have this field set to the old TSS selector.
The new task is said to be nested.
The CPU will also use the NT (Nested Task) flag to keep track of whenever the current task is nested or not.

If a task is nested (i.e. invoked with call, int, and interrupt or an exception), using the iret instruction the CPU will read the Previous Task Link to find the suspended Task to resume.

Note that only iret can be used, even if the task switching was done with call (which normally pairs with ret/retf).

This is a picture from the Manual:

Your guess seems right. The code tries to set random colors. As it is part of a 256-byte intro, the focus is primarily on code size, not on portability or quality of the random numbers. Possibly this executable was originally meant for a PS/2 or EISA system, and timers 0, 3 and 5 (channel 0 and 2 of the second chip) were free-running. In case you don't have an EISA system, often aliasing will access timers 0, 0 again and 2. This program doesn't enable sound, so timer 2 would be stuck. Furthermore, the code clobbers AH as generated by the DIV instruction at 1BE by executing a MUL instruction at 1CA, so the value read from port 40h isn't used.

To undestand more than this educated guesswork, you would need to contact the author of that code. Considering the bug that AH is clobbered, it seems the code has been created at a demo party under time pressure, and not a lot of "design" went into it. It seems more like "it works well enough".

To fix that bug the image should have 515585 bytes or more, I don't know where this number comes from, I have tested several combinations until achieve this result, if you try one single byte less it doesn't work, but more bytes works fine.